[PATCH V4 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table

2016-11-07 Thread Mirza Krak
From: Mirza Krak Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which is max rate. The maximum rate value of 127 MHz is pulled from the downstream L4T kernel. Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Bo

Re: [PATCH V4 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table

2016-11-07 Thread Thierry Reding
On Mon, Nov 07, 2016 at 09:30:01AM +0100, Mirza Krak wrote: > From: Mirza Krak > > Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which > is max rate. > > The maximum rate value of 127 MHz is pulled from the downstream L4T > kernel. > > Signed-off-by: Mirza Krak > Tested-by: