Hi, Argus
On Wed, 2018-05-02 at 17:21 +0800, argus....@mediatek.com wrote:
> From: Argus Lin <argus....@mediatek.com>
>
> mt6351 is a new power management IC and it is
> used for mt6797 SoCs. We need to add mt6351_regs for
> pmic register mapping and pmic_mt6351 for
> register accessing by regmap.
>
suggest line wrapping closely at 75 columns
> Signed-off-by: Argus Lin <argus....@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-pmic-wrap.c | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c
> b/drivers/soc/mediatek/mtk-pmic-wrap.c
> index 285bfa76249f..26076900eee0 100644
> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> @@ -152,6 +152,21 @@ static const u32 mt6397_regs[] = {
> [PWRAP_DEW_CIPHER_SWRST] = 0xbc24,
> };
>
> +static const u32 mt6351_regs[] = {
> + [PWRAP_DEW_DIO_EN] = 0x02F2,
> + [PWRAP_DEW_READ_TEST] = 0x02F4,
> + [PWRAP_DEW_WRITE_TEST] = 0x02F6,
> + [PWRAP_DEW_CRC_EN] = 0x02FA,
> + [PWRAP_DEW_CRC_VAL] = 0x02FC,
> + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0300,
> + [PWRAP_DEW_CIPHER_IV_SEL] = 0x0302,
> + [PWRAP_DEW_CIPHER_EN] = 0x0304,
> + [PWRAP_DEW_CIPHER_RDY] = 0x0306,
> + [PWRAP_DEW_CIPHER_MODE] = 0x0308,
> + [PWRAP_DEW_CIPHER_SWRST] = 0x030A,
> + [PWRAP_DEW_RDDMY_NO] = 0x030C,
> +};
> +
trim the unused registers if any
> enum pwrap_regs {
> PWRAP_MUX_SEL,
> PWRAP_WRAP_EN,
> @@ -684,6 +699,7 @@ static int mt8135_regs[] = {
>
> enum pmic_type {
> PMIC_MT6323,
> + PMIC_MT6351,
> PMIC_MT6380,
> PMIC_MT6397,
> };
> @@ -1150,6 +1166,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
> 0x1);
> break;
> case PMIC_MT6323:
> + case PMIC_MT6351:
> pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
> 0x1);
> break;
> @@ -1435,6 +1452,15 @@ static const struct pwrap_slv_type pmic_mt6397 = {
> .pwrap_write = pwrap_write16,
> };
>
> +static const struct pwrap_slv_type pmic_mt6351 = {
> + .dew_regs = mt6351_regs,
> + .type = PMIC_MT6351,
> + .regmap = &pwrap_regmap_config16,
> + .caps = 0,
the caps should be
PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
PWRAP_SLV_CAP_SECURITY,
otherwise, the registers you defined here cannot be accessed by its
function.
> + .pwrap_read = pwrap_read16,
> + .pwrap_write = pwrap_write16,
> +};
> +
> static const struct of_device_id of_slave_match_tbl[] = {
> {
> .compatible = "mediatek,mt6323",
> @@ -1449,6 +1475,9 @@ static const struct of_device_id of_slave_match_tbl[] =
> {
> .compatible = "mediatek,mt6397",
> .data = &pmic_mt6397,
> }, {
> + .compatible = "mediatek,mt6351",
> + .data = &pmic_mt6351,
> + }, {
need to be sorted din alphabetical order
> /* sentinel */
> }
> };
