Re: [PATCH V5 08/25] perf/x86: Hybrid PMU support for hardware cache event

On Mon, Apr 05, 2021 at 08:10:50AM -0700, kan.li...@linux.intel.com wrote: > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c > index 0bd9554..d71ca69 100644 > --- a/arch/x86/events/core.c > +++ b/arch/x86/events/core.c > @@ -356,6 +356,7 @@ set_ext_hw_attr(struct hw_perf_event *hwc, st

[PATCH V5 08/25] perf/x86: Hybrid PMU support for hardware cache event

From: Kan Liang The hardware cache events are different among hybrid PMUs. Each hybrid PMU should have its own hw cache event table. The hw_cache_extra_regs is not part of the struct x86_pmu, the hybrid() cannot be applied here. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86/e