2014-12-20 4:44 GMT-08:00 Jonas Gorski :
> On Sat, Dec 20, 2014 at 2:39 AM, Kevin Cernekee wrote:
>> On Mon, Dec 15, 2014 at 1:43 AM, Jonas Gorski wrote:
>>> On Fri, Dec 12, 2014 at 11:07 PM, Kevin Cernekee wrote:
BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
t
On Sat, Dec 20, 2014 at 4:44 AM, Jonas Gorski wrote:
> On Sat, Dec 20, 2014 at 2:39 AM, Kevin Cernekee wrote:
>> On Mon, Dec 15, 2014 at 1:43 AM, Jonas Gorski wrote:
>>> On Fri, Dec 12, 2014 at 11:07 PM, Kevin Cernekee wrote:
BMIPS 3300/435x/438x CPUs have a readahead cache that is separat
On Sat, Dec 20, 2014 at 2:39 AM, Kevin Cernekee wrote:
> On Mon, Dec 15, 2014 at 1:43 AM, Jonas Gorski wrote:
>> On Fri, Dec 12, 2014 at 11:07 PM, Kevin Cernekee wrote:
>>> BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
>>> the L1/L2. During a DMA operation, accesses adj
On Mon, Dec 15, 2014 at 1:43 AM, Jonas Gorski wrote:
> On Fri, Dec 12, 2014 at 11:07 PM, Kevin Cernekee wrote:
>> BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
>> the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer
>> may cause parts of the DMA buffer to
On Fri, Dec 12, 2014 at 11:07 PM, Kevin Cernekee wrote:
> BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
> the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer
> may cause parts of the DMA buffer to be prefetched into the RAC. To
> avoid possible coherency
BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer
may cause parts of the DMA buffer to be prefetched into the RAC. To
avoid possible coherency problems, flush the RAC upon DMA completion.
Signed-off-by: Kev
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