Re: [PATCH V5 13/23] MIPS: BMIPS: Flush the readahead cache after DMA

2014-12-21 Thread Florian Fainelli
2014-12-20 4:44 GMT-08:00 Jonas Gorski : > On Sat, Dec 20, 2014 at 2:39 AM, Kevin Cernekee wrote: >> On Mon, Dec 15, 2014 at 1:43 AM, Jonas Gorski wrote: >>> On Fri, Dec 12, 2014 at 11:07 PM, Kevin Cernekee wrote: BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from t

Re: [PATCH V5 13/23] MIPS: BMIPS: Flush the readahead cache after DMA

2014-12-20 Thread Kevin Cernekee
On Sat, Dec 20, 2014 at 4:44 AM, Jonas Gorski wrote: > On Sat, Dec 20, 2014 at 2:39 AM, Kevin Cernekee wrote: >> On Mon, Dec 15, 2014 at 1:43 AM, Jonas Gorski wrote: >>> On Fri, Dec 12, 2014 at 11:07 PM, Kevin Cernekee wrote: BMIPS 3300/435x/438x CPUs have a readahead cache that is separat

Re: [PATCH V5 13/23] MIPS: BMIPS: Flush the readahead cache after DMA

2014-12-20 Thread Jonas Gorski
On Sat, Dec 20, 2014 at 2:39 AM, Kevin Cernekee wrote: > On Mon, Dec 15, 2014 at 1:43 AM, Jonas Gorski wrote: >> On Fri, Dec 12, 2014 at 11:07 PM, Kevin Cernekee wrote: >>> BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from >>> the L1/L2. During a DMA operation, accesses adj

Re: [PATCH V5 13/23] MIPS: BMIPS: Flush the readahead cache after DMA

2014-12-19 Thread Kevin Cernekee
On Mon, Dec 15, 2014 at 1:43 AM, Jonas Gorski wrote: > On Fri, Dec 12, 2014 at 11:07 PM, Kevin Cernekee wrote: >> BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from >> the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer >> may cause parts of the DMA buffer to

Re: [PATCH V5 13/23] MIPS: BMIPS: Flush the readahead cache after DMA

2014-12-15 Thread Jonas Gorski
On Fri, Dec 12, 2014 at 11:07 PM, Kevin Cernekee wrote: > BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from > the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer > may cause parts of the DMA buffer to be prefetched into the RAC. To > avoid possible coherency

[PATCH V5 13/23] MIPS: BMIPS: Flush the readahead cache after DMA

2014-12-12 Thread Kevin Cernekee
BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer may cause parts of the DMA buffer to be prefetched into the RAC. To avoid possible coherency problems, flush the RAC upon DMA completion. Signed-off-by: Kev