Re: [PATCH V6 00/18] x86: Full support of PAT

2014-11-16 Thread Jürgen Groß
On 11/16/2014 02:08 PM, Ingo Molnar wrote: * Juergen Gross wrote: arch/x86/include/asm/cacheflush.h | 38 --- FYI, this series breaks the UML build: In file included from /home/mingo/tip/include/linux/highmem.h:11:0, from /home/mingo/tip/include/linux/pagema

Re: [PATCH V6 00/18] x86: Full support of PAT

2014-11-16 Thread Ingo Molnar
* Juergen Gross wrote: > arch/x86/include/asm/cacheflush.h | 38 --- FYI, this series breaks the UML build: In file included from /home/mingo/tip/include/linux/highmem.h:11:0, from /home/mingo/tip/include/linux/pagemap.h:10, from /home/mingo/tip/i

Re: [PATCH V6 00/18] x86: Full support of PAT

2014-11-13 Thread Juergen Gross
Ingo, could you take the patches, please? Juergen On 11/03/2014 02:01 PM, Juergen Gross wrote: The x86 architecture offers via the PAT (Page Attribute Table) a way to specify different caching modes in page table entries. The PAT MSR contains 8 entries each specifying one of 6 possible cache

Re: [PATCH V6 00/18] x86: Full support of PAT

2014-11-03 Thread Toshi Kani
On Mon, 2014-11-03 at 14:01 +0100, Juergen Gross wrote: > The x86 architecture offers via the PAT (Page Attribute Table) a way to > specify different caching modes in page table entries. The PAT MSR contains > 8 entries each specifying one of 6 possible cache modes. A pte references one > of those

[PATCH V6 00/18] x86: Full support of PAT

2014-11-03 Thread Juergen Gross
The x86 architecture offers via the PAT (Page Attribute Table) a way to specify different caching modes in page table entries. The PAT MSR contains 8 entries each specifying one of 6 possible cache modes. A pte references one of those entries via 3 bits: _PAGE_PAT, _PAGE_PWT and _PAGE_PCD. The Lin