On Tue, Jul 21, 2020 at 10:05:55AM -0400, Liang, Kan wrote:
> On 7/21/2020 5:43 AM, Peter Zijlstra wrote:
> > @@ -1098,37 +1105,20 @@ static int collect_events(struct cpu_hw_
> > cpuc->pebs_output = is_pebs_pt(leader) + 1;
> > }
> > - if (x86_pmu.intel_cap.perf_metrics &&
> > -
On 7/21/2020 5:43 AM, Peter Zijlstra wrote:
On Fri, Jul 17, 2020 at 07:05:47AM -0700, kan.li...@linux.intel.com wrote:
@@ -1031,6 +1034,35 @@ int x86_schedule_events(struct cpu_hw_events *cpuc, int
n, int *assign)
return unsched ? -EINVAL : 0;
}
+static int
On Fri, Jul 17, 2020 at 07:05:47AM -0700, kan.li...@linux.intel.com wrote:
> @@ -1031,6 +1034,35 @@ int x86_schedule_events(struct cpu_hw_events *cpuc,
> int n, int *assign)
> return unsched ? -EINVAL : 0;
> }
>
> +static int add_nr_metric_event(struct cpu_hw_events *cpuc,
> +
On 7/20/2020 1:41 PM, Peter Zijlstra wrote:
On Fri, Jul 17, 2020 at 07:05:47AM -0700, kan.li...@linux.intel.com wrote:
For the event mapping, a special 0x00 event code is used, which is
reserved for fake events. The metric events start from umask 0x10.
+#define INTEL_PMC_IDX_METRIC_BASE
On Fri, Jul 17, 2020 at 07:05:47AM -0700, kan.li...@linux.intel.com wrote:
> For the event mapping, a special 0x00 event code is used, which is
> reserved for fake events. The metric events start from umask 0x10.
> +#define INTEL_PMC_IDX_METRIC_BASE(INTEL_PMC_IDX_FIXED + 16)
>
From: Kan Liang
Intro
=
The TopDown Microarchitecture Analysis (TMA) Method is a structured
analysis methodology to identify critical performance bottlenecks in
out-of-order processors. Current perf has supported the method.
The method works well, but there is one problem. To collect the
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