On Fri, 4 Oct 2019 at 14:59, Ludovic BARRE wrote:
>
> hi Ulf
>
> Le 10/4/19 à 8:20 AM, Ulf Hansson a écrit :
> > On Fri, 4 Oct 2019 at 08:12, Ulf Hansson wrote:
> >>
> >> On Thu, 5 Sep 2019 at 14:21, Ludovic Barre wrote:
> >>>
> >>> From: Ludovic Barre
> >>>
> >>> In some variants, the data tim
hi Ulf
Le 10/4/19 à 8:20 AM, Ulf Hansson a écrit :
On Fri, 4 Oct 2019 at 08:12, Ulf Hansson wrote:
On Thu, 5 Sep 2019 at 14:21, Ludovic Barre wrote:
From: Ludovic Barre
In some variants, the data timer starts and decrements
when the DPSM enters in Wait_R or Busy state
(while data transfe
On Fri, 4 Oct 2019 at 08:12, Ulf Hansson wrote:
>
> On Thu, 5 Sep 2019 at 14:21, Ludovic Barre wrote:
> >
> > From: Ludovic Barre
> >
> > In some variants, the data timer starts and decrements
> > when the DPSM enters in Wait_R or Busy state
> > (while data transfer or MMC_RSP_BUSY), and generat
On Thu, 5 Sep 2019 at 14:21, Ludovic Barre wrote:
>
> From: Ludovic Barre
>
> In some variants, the data timer starts and decrements
> when the DPSM enters in Wait_R or Busy state
> (while data transfer or MMC_RSP_BUSY), and generates a
> data timeout error if the counter reach 0.
>
> -Define m
From: Ludovic Barre
In some variants, the data timer starts and decrements
when the DPSM enters in Wait_R or Busy state
(while data transfer or MMC_RSP_BUSY), and generates a
data timeout error if the counter reach 0.
-Define max_busy_timeout (in ms) according to clock.
-Set data timer register
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