On 13/02/2017 15:17, zhichang.yuan wrote:
Hi, Alex,
On 2017/2/1 3:37, Alexander Graf wrote:
On 31/01/2017 14:32, John Garry wrote:
On 30/01/2017 17:12, Alexander Graf wrote:
On 01/24/2017 08:05 AM, zhichang.yuan wrote:
Low-pin-count interface is integrated into some SoCs. The accesses t
On 13/02/2017 15:05, zhichang.yuan wrote:
Hi, Alex,
Thanks for your review!
Sorry for the late response!
As this patch-set was two weeks ago, it must be painful to check this thread
again.
I thought John had discussed with you about most of the comments when I was
back from ten days' leave,
Hi, Alex,
On 2017/2/1 3:37, Alexander Graf wrote:
>
>
> On 31/01/2017 14:32, John Garry wrote:
>> On 30/01/2017 17:12, Alexander Graf wrote:
>>> On 01/24/2017 08:05 AM, zhichang.yuan wrote:
Low-pin-count interface is integrated into some SoCs. The accesses to
those
peripherals un
Hi, Alex,
Thanks for your review!
Sorry for the late response!
As this patch-set was two weeks ago, it must be painful to check this thread
again.
I thought John had discussed with you about most of the comments when I was
back from ten days' leave, and I have no more to supplement,
so...
But w
Hi Alex
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
[...]
> >>
> >> I like the extio idea. That allows us to handle all PIO requests on
> >> platforms that don't have native PIO support via different routes
> >> depending on the region they're in. Unfortunately we
On 31/01/2017 14:32, John Garry wrote:
On 30/01/2017 17:12, Alexander Graf wrote:
On 01/24/2017 08:05 AM, zhichang.yuan wrote:
Low-pin-count interface is integrated into some SoCs. The accesses to
those
peripherals under LPC make use of I/O ports rather than the memory
mapped I/O.
To drive t
On 31/01/2017 00:09, Bjorn Helgaas wrote:
On Tue, Jan 24, 2017 at 03:05:21PM +0800, zhichang.yuan wrote:
Low-pin-count interface is integrated into some SoCs. The accesses to those
peripherals under LPC make use of I/O ports rather than the memory mapped I/O.
To drive these devices, this patch
On 30/01/2017 17:12, Alexander Graf wrote:
On 01/24/2017 08:05 AM, zhichang.yuan wrote:
Low-pin-count interface is integrated into some SoCs. The accesses to
those
peripherals under LPC make use of I/O ports rather than the memory
mapped I/O.
To drive these devices, this patch introduces a meth
On Tue, Jan 24, 2017 at 03:05:21PM +0800, zhichang.yuan wrote:
> Low-pin-count interface is integrated into some SoCs. The accesses to those
> peripherals under LPC make use of I/O ports rather than the memory mapped I/O.
>
> To drive these devices, this patch introduces a method named indirect-IO
On 01/24/2017 08:05 AM, zhichang.yuan wrote:
Low-pin-count interface is integrated into some SoCs. The accesses to those
peripherals under LPC make use of I/O ports rather than the memory mapped I/O.
To drive these devices, this patch introduces a method named indirect-IO.
In this method the in/
Low-pin-count interface is integrated into some SoCs. The accesses to those
peripherals under LPC make use of I/O ports rather than the memory mapped I/O.
To drive these devices, this patch introduces a method named indirect-IO.
In this method the in/out() accessor in include/asm-generic/io.h will
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