On 7/28/2020 9:44 AM, pet...@infradead.org wrote:
On Tue, Jul 28, 2020 at 09:28:39AM -0400, Liang, Kan wrote:
On 7/28/2020 9:09 AM, Peter Zijlstra wrote:
On Fri, Jul 24, 2020 at 03:10:52PM -0400, Liang, Kan wrote:
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
i
On Tue, Jul 28, 2020 at 09:28:39AM -0400, Liang, Kan wrote:
>
>
> On 7/28/2020 9:09 AM, Peter Zijlstra wrote:
> > On Fri, Jul 24, 2020 at 03:10:52PM -0400, Liang, Kan wrote:
> >
> > > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> > > index 6cb079e0c9d9..010ac74afc09
On 7/28/2020 9:09 AM, Peter Zijlstra wrote:
On Fri, Jul 24, 2020 at 03:10:52PM -0400, Liang, Kan wrote:
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 6cb079e0c9d9..010ac74afc09 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2
On Fri, Jul 24, 2020 at 03:10:52PM -0400, Liang, Kan wrote:
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 6cb079e0c9d9..010ac74afc09 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -2405,27 +2405,18 @@ static u64 icl_update
On Fri, Jul 24, 2020 at 03:10:52PM -0400, Liang, Kan wrote:
> > > > Per the SIBLING patch this then wants to be:
> > > >
> > > > if (!is_slots_event(leader))
> > > > return -EINVAL;
> > > >
> > > > event->event_caps |= PERF_EV_CAP_SIBLING.
> > > >
On 7/24/2020 12:07 PM, Liang, Kan wrote:
On 7/24/2020 11:27 AM, pet...@infradead.org wrote:
On Fri, Jul 24, 2020 at 03:19:06PM +0200, pet...@infradead.org wrote:
On Thu, Jul 23, 2020 at 10:11:11AM -0700, kan.li...@linux.intel.com
wrote:
@@ -3375,6 +3428,72 @@ static int intel_pmu_hw_config
On 7/24/2020 11:27 AM, pet...@infradead.org wrote:
On Fri, Jul 24, 2020 at 03:19:06PM +0200, pet...@infradead.org wrote:
On Thu, Jul 23, 2020 at 10:11:11AM -0700, kan.li...@linux.intel.com wrote:
@@ -3375,6 +3428,72 @@ static int intel_pmu_hw_config(struct perf_event *event)
if (even
On Fri, Jul 24, 2020 at 03:19:06PM +0200, pet...@infradead.org wrote:
> On Thu, Jul 23, 2020 at 10:11:11AM -0700, kan.li...@linux.intel.com wrote:
> > @@ -3375,6 +3428,72 @@ static int intel_pmu_hw_config(struct perf_event
> > *event)
> > if (event->attr.type != PERF_TYPE_RAW)
> >
On Thu, Jul 23, 2020 at 10:11:11AM -0700, kan.li...@linux.intel.com wrote:
> @@ -3375,6 +3428,72 @@ static int intel_pmu_hw_config(struct perf_event
> *event)
> if (event->attr.type != PERF_TYPE_RAW)
> return 0;
>
> + /*
> + * Config Topdown slots and metric events
>
From: Kan Liang
Intro
=
The TopDown Microarchitecture Analysis (TMA) Method is a structured
analysis methodology to identify critical performance bottlenecks in
out-of-order processors. Current perf has supported the method.
The method works well, but there is one problem. To collect the To
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