On Tue, Oct 16, 2018 at 05:00:03PM -0700, Joel Fernandes (Google) wrote:
> From: Pierre Yves MORDRET
>
> commit e57cb3b3f10d005410f09d4598cc6d62b833f2b0 upstream.
>
> When in cyclic mode, the configuration is updated after having started the
> DMA hardware (STM32_DMA_SCR_EN) leading to
On Tue, Oct 16, 2018 at 05:00:03PM -0700, Joel Fernandes (Google) wrote:
> From: Pierre Yves MORDRET
>
> commit e57cb3b3f10d005410f09d4598cc6d62b833f2b0 upstream.
>
> When in cyclic mode, the configuration is updated after having started the
> DMA hardware (STM32_DMA_SCR_EN) leading to
From: Pierre Yves MORDRET
commit e57cb3b3f10d005410f09d4598cc6d62b833f2b0 upstream.
When in cyclic mode, the configuration is updated after having started the
DMA hardware (STM32_DMA_SCR_EN) leading to incomplete configuration of
SMxAR registers.
Signed-off-by: Pierre-Yves MORDRET
From: Pierre Yves MORDRET
commit e57cb3b3f10d005410f09d4598cc6d62b833f2b0 upstream.
When in cyclic mode, the configuration is updated after having started the
DMA hardware (STM32_DMA_SCR_EN) leading to incomplete configuration of
SMxAR registers.
Signed-off-by: Pierre-Yves MORDRET
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