On Thu, May 14, 2020 at 06:01:52PM +0200, Andrew Lunn wrote:
> On Thu, May 14, 2020 at 03:47:16PM +, Christian Herber wrote:
> > Hi Andrew,
> >
> > > On Wed, May 13, 2020 at 03:39:00PM +0200, Andrew Lunn wrote:
> > >> On Thu, May 14, 2020 at 02:09:59PM +0200, Oleksij Rempel wrote:
> > >>
On Thu, May 14, 2020 at 03:47:16PM +, Christian Herber wrote:
> Hi Andrew,
>
> > On Wed, May 13, 2020 at 03:39:00PM +0200, Andrew Lunn wrote:
> >> On Thu, May 14, 2020 at 02:09:59PM +0200, Oleksij Rempel wrote:
> >> ETHTOOL_A_CABLE_RESULT_CODE_ACTIVE_PARTNER - the link partner is active.
>
Hi Andrew,
> On Wed, May 13, 2020 at 03:39:00PM +0200, Andrew Lunn wrote:
>> On Thu, May 14, 2020 at 02:09:59PM +0200, Oleksij Rempel wrote:
>> ETHTOOL_A_CABLE_RESULT_CODE_ACTIVE_PARTNER - the link partner is active.
>>
>> The TJA1102 is able to detect it if partner link is master.
>>
>
On Thu, May 14, 2020 at 02:09:59PM +0200, Oleksij Rempel wrote:
> On Wed, May 13, 2020 at 08:01:40PM +0200, Andrew Lunn wrote:
> > > What would be the best place to do a test before the link is getting up?
> > > Can it be done in the phy core, or it should be done in the PHY driver?
> > >
> > >
On Wed, May 13, 2020 at 08:01:40PM +0200, Andrew Lunn wrote:
> > What would be the best place to do a test before the link is getting up?
> > Can it be done in the phy core, or it should be done in the PHY driver?
> >
> > So far, no action except of logging these errors is needed.
>
> You could
From: Oleksij Rempel
Date: Wed, 13 May 2020 14:34:40 +0200
> Add initial cable testing support.
> This PHY needs only 100usec for this test and it is recommended to run it
> before the link is up. For now, provide at least ethtool support, so it
> can be tested by more developers.
>
> This
On 5/13/2020 5:34 AM, Oleksij Rempel wrote:
> Add initial cable testing support.
> This PHY needs only 100usec for this test and it is recommended to run it
> before the link is up. For now, provide at least ethtool support, so it
> can be tested by more developers.
>
> This patch was tested
> > Do these registers all conform to the standard? Can we pull this code
> > out into a library which all standards conformant PHY drivers can use?
>
> According to opensig, this functionality should be present on all new T1 PHYs.
> But the register/bit layout is no specified as standard. At
> What would be the best place to do a test before the link is getting up?
> Can it be done in the phy core, or it should be done in the PHY driver?
>
> So far, no action except of logging these errors is needed.
You could do it in the config_aneg callback.
A kernel log entry is not very easy
On Wed, May 13, 2020 at 03:39:25PM +0200, Andrew Lunn wrote:
> On Wed, May 13, 2020 at 02:34:40PM +0200, Oleksij Rempel wrote:
> > Add initial cable testing support.
> > This PHY needs only 100usec for this test and it is recommended to run it
> > before the link is up. For now, provide at least
On Wed, May 13, 2020 at 02:34:40PM +0200, Oleksij Rempel wrote:
> Add initial cable testing support.
> This PHY needs only 100usec for this test and it is recommended to run it
> before the link is up. For now, provide at least ethtool support, so it
> can be tested by more developers.
>
> This
Add initial cable testing support.
This PHY needs only 100usec for this test and it is recommended to run it
before the link is up. For now, provide at least ethtool support, so it
can be tested by more developers.
This patch was tested with TJA1102 PHY with following results:
- No cable, is
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