Re: [PATCH resend] clk: si5351: Wait for bit clear after PLL reset

Quoting Sascha Hauer (2020-11-30 01:10:33) > Documentation states that SI5351_PLL_RESET_B and SI5351_PLL_RESET_A bits > are self clearing bits, so wait until they are cleared before > continuing. > This fixes a case when the clock doesn't come up properly after a PLL > reset. It worked properly whe

[PATCH resend] clk: si5351: Wait for bit clear after PLL reset

Documentation states that SI5351_PLL_RESET_B and SI5351_PLL_RESET_A bits are self clearing bits, so wait until they are cleared before continuing. This fixes a case when the clock doesn't come up properly after a PLL reset. It worked properly when the frequency was below 900MHz, but with 900MHz it