Re: [PATCH v1] PCI: Fixup the RTIT_BAR of Intel TH on Denverton

2017-10-26 Thread Bjorn Helgaas
On Thu, Oct 26, 2017 at 05:28:17PM +0300, Alexander Shishkin wrote: > On some integrations of the Intel(R) Trace Hub (for a reference and > overview see Documentation/trace/intel_th.txt) the reported size of > one of its resources (RTIT_BAR) doesn't match its actual size, which > leads to overlaps

[PATCH v1] PCI: Fixup the RTIT_BAR of Intel TH on Denverton

2017-10-26 Thread Alexander Shishkin
On some integrations of the Intel(R) Trace Hub (for a reference and overview see Documentation/trace/intel_th.txt) the reported size of one of its resources (RTIT_BAR) doesn't match its actual size, which leads to overlaps with other devices' resources. On a Denverton platform it overlaps with XHC