Re: [PATCH v1] clk: tegra20: Add 216 MHz entry for PLL_X

2017-12-12 Thread Dmitry Osipenko
On 12.12.2017 18:17, Peter De Schrijver wrote: > On Tue, Dec 12, 2017 at 03:08:08PM +0300, Dmitry Osipenko wrote: >> On 12.12.2017 13:02, Peter De Schrijver wrote: >>> On Mon, Dec 11, 2017 at 09:50:09PM +0300, Dmitry Osipenko wrote: The cpufreq driver uses 216 MHz as the lowest CPU clock

Re: [PATCH v1] clk: tegra20: Add 216 MHz entry for PLL_X

2017-12-12 Thread Dmitry Osipenko
On 12.12.2017 18:17, Peter De Schrijver wrote: > On Tue, Dec 12, 2017 at 03:08:08PM +0300, Dmitry Osipenko wrote: >> On 12.12.2017 13:02, Peter De Schrijver wrote: >>> On Mon, Dec 11, 2017 at 09:50:09PM +0300, Dmitry Osipenko wrote: The cpufreq driver uses 216 MHz as the lowest CPU clock

Re: [PATCH v1] clk: tegra20: Add 216 MHz entry for PLL_X

2017-12-12 Thread Peter De Schrijver
On Tue, Dec 12, 2017 at 03:08:08PM +0300, Dmitry Osipenko wrote: > On 12.12.2017 13:02, Peter De Schrijver wrote: > > On Mon, Dec 11, 2017 at 09:50:09PM +0300, Dmitry Osipenko wrote: > >> The cpufreq driver uses 216 MHz as the lowest CPU clock frequency, but > >> clock driver doesn't provide that

Re: [PATCH v1] clk: tegra20: Add 216 MHz entry for PLL_X

2017-12-12 Thread Peter De Schrijver
On Tue, Dec 12, 2017 at 03:08:08PM +0300, Dmitry Osipenko wrote: > On 12.12.2017 13:02, Peter De Schrijver wrote: > > On Mon, Dec 11, 2017 at 09:50:09PM +0300, Dmitry Osipenko wrote: > >> The cpufreq driver uses 216 MHz as the lowest CPU clock frequency, but > >> clock driver doesn't provide that

Re: [PATCH v1] clk: tegra20: Add 216 MHz entry for PLL_X

2017-12-12 Thread Dmitry Osipenko
On 12.12.2017 13:02, Peter De Schrijver wrote: > On Mon, Dec 11, 2017 at 09:50:09PM +0300, Dmitry Osipenko wrote: >> The cpufreq driver uses 216 MHz as the lowest CPU clock frequency, but >> clock driver doesn't provide that rate, so the requested clock is rounded >> up to 312 MHz. Let's add entry

Re: [PATCH v1] clk: tegra20: Add 216 MHz entry for PLL_X

2017-12-12 Thread Dmitry Osipenko
On 12.12.2017 13:02, Peter De Schrijver wrote: > On Mon, Dec 11, 2017 at 09:50:09PM +0300, Dmitry Osipenko wrote: >> The cpufreq driver uses 216 MHz as the lowest CPU clock frequency, but >> clock driver doesn't provide that rate, so the requested clock is rounded >> up to 312 MHz. Let's add entry

Re: [PATCH v1] clk: tegra20: Add 216 MHz entry for PLL_X

2017-12-12 Thread Peter De Schrijver
On Mon, Dec 11, 2017 at 09:50:09PM +0300, Dmitry Osipenko wrote: > The cpufreq driver uses 216 MHz as the lowest CPU clock frequency, but > clock driver doesn't provide that rate, so the requested clock is rounded > up to 312 MHz. Let's add entry for 216 MHz to match with cpufreq. > This seems

Re: [PATCH v1] clk: tegra20: Add 216 MHz entry for PLL_X

2017-12-12 Thread Peter De Schrijver
On Mon, Dec 11, 2017 at 09:50:09PM +0300, Dmitry Osipenko wrote: > The cpufreq driver uses 216 MHz as the lowest CPU clock frequency, but > clock driver doesn't provide that rate, so the requested clock is rounded > up to 312 MHz. Let's add entry for 216 MHz to match with cpufreq. > This seems

[PATCH v1] clk: tegra20: Add 216 MHz entry for PLL_X

2017-12-11 Thread Dmitry Osipenko
The cpufreq driver uses 216 MHz as the lowest CPU clock frequency, but clock driver doesn't provide that rate, so the requested clock is rounded up to 312 MHz. Let's add entry for 216 MHz to match with cpufreq. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20.c

[PATCH v1] clk: tegra20: Add 216 MHz entry for PLL_X

2017-12-11 Thread Dmitry Osipenko
The cpufreq driver uses 216 MHz as the lowest CPU clock frequency, but clock driver doesn't provide that rate, so the requested clock is rounded up to 312 MHz. Let's add entry for 216 MHz to match with cpufreq. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20.c | 5 + 1 file