Re: [PATCH v1 1/3] arm: mm: reordering memory type table

2018-09-28 Thread Minchan Kim
Hi Catalin, Sorry for the late response. It was big holiday here. I will correct what you pointed out and resubmit patch next week. Thanks for the review! On Mon, Sep 24, 2018 at 05:22:03PM +0100, Catalin Marinas wrote: > On Mon, Sep 17, 2018 at 09:44:49AM +0900, Minchan Kim wrote: > > To use

Re: [PATCH v1 1/3] arm: mm: reordering memory type table

2018-09-28 Thread Minchan Kim
Hi Catalin, Sorry for the late response. It was big holiday here. I will correct what you pointed out and resubmit patch next week. Thanks for the review! On Mon, Sep 24, 2018 at 05:22:03PM +0100, Catalin Marinas wrote: > On Mon, Sep 17, 2018 at 09:44:49AM +0900, Minchan Kim wrote: > > To use

Re: [PATCH v1 1/3] arm: mm: reordering memory type table

2018-09-24 Thread Catalin Marinas
On Mon, Sep 17, 2018 at 09:44:49AM +0900, Minchan Kim wrote: > To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that. > It seems we don't need 4 bits for the memory type with ARMv6+. > If it's true, let's reorder bits to make bit 5 free. > > We will use the bit for L_PTE_SPECIAL in

Re: [PATCH v1 1/3] arm: mm: reordering memory type table

2018-09-24 Thread Catalin Marinas
On Mon, Sep 17, 2018 at 09:44:49AM +0900, Minchan Kim wrote: > To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that. > It seems we don't need 4 bits for the memory type with ARMv6+. > If it's true, let's reorder bits to make bit 5 free. > > We will use the bit for L_PTE_SPECIAL in

Re: [PATCH v1 1/3] arm: mm: reordering memory type table

2018-09-20 Thread Minchan Kim
Hi Guys, Could you have a chance to review this patchset? Thanks! On Mon, Sep 17, 2018 at 09:44:49AM +0900, Minchan Kim wrote: > To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that. > It seems we don't need 4 bits for the memory type with ARMv6+. > If it's true, let's reorder

Re: [PATCH v1 1/3] arm: mm: reordering memory type table

2018-09-20 Thread Minchan Kim
Hi Guys, Could you have a chance to review this patchset? Thanks! On Mon, Sep 17, 2018 at 09:44:49AM +0900, Minchan Kim wrote: > To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that. > It seems we don't need 4 bits for the memory type with ARMv6+. > If it's true, let's reorder

[PATCH v1 1/3] arm: mm: reordering memory type table

2018-09-16 Thread Minchan Kim
To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that. It seems we don't need 4 bits for the memory type with ARMv6+. If it's true, let's reorder bits to make bit 5 free. We will use the bit for L_PTE_SPECIAL in next patch. A note from Catalin " > Anyway, on ARMv7 or ARMv6+LPAE,

[PATCH v1 1/3] arm: mm: reordering memory type table

2018-09-16 Thread Minchan Kim
To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that. It seems we don't need 4 bits for the memory type with ARMv6+. If it's true, let's reorder bits to make bit 5 free. We will use the bit for L_PTE_SPECIAL in next patch. A note from Catalin " > Anyway, on ARMv7 or ARMv6+LPAE,