Hanks,
On Tue, Dec 01 2020 at 21:54, Hanks Chen wrote:
> On Fri, 2020-11-27 at 18:11 +, Marc Zyngier wrote:
>> On 2020-11-27 14:15, Hanks Chen wrote:
>> > + /*
>> > + * No move required, if interrupt is 1 of N IRQ.
>> > + * write current cpu_online_mask into affinity mask.
>> > + */
>>
Hi Marc,
Sorry for the late reply.
On Fri, 2020-11-27 at 18:11 +, Marc Zyngier wrote:
> On 2020-11-27 14:15, Hanks Chen wrote:
> > Support for interrupt distribution design for SMP system solutions.
>
> As far as I know, we have been supporting interrupt distribution on
> ARM SMP systems
On 2020-11-27 18:56, Catalin Marinas wrote:
On Fri, Nov 27, 2020 at 06:11:01PM +, Marc Zyngier wrote:
On 2020-11-27 14:15, Hanks Chen wrote:
> Support for interrupt distribution design for SMP system solutions.
As far as I know, we have been supporting interrupt distribution on
ARM SMP
On Fri, Nov 27, 2020 at 06:11:01PM +, Marc Zyngier wrote:
> On 2020-11-27 14:15, Hanks Chen wrote:
> > Support for interrupt distribution design for SMP system solutions.
>
> As far as I know, we have been supporting interrupt distribution on
> ARM SMP systems pretty well for the past...
On 2020-11-27 14:15, Hanks Chen wrote:
Support for interrupt distribution design for SMP system solutions.
As far as I know, we have been supporting interrupt distribution on
ARM SMP systems pretty well for the past... what... 15 years?
I'm sure Russell can dig out an ARM926 SMP system that
Support for interrupt distribution design for SMP system solutions.
With this feature enabled ,the SPI interrupts would be routed to
all the cores rather than boot core to achieve better
load balance of interrupt handling.
That is, interrupts might be serviced simultaneously on different CPUs.
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