Re: [PATCH v1 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers

2018-05-03 Thread Dmitry Osipenko
On 03.05.2018 15:30, Marcel Ziswiler wrote: > On Thu, 2018-05-03 at 15:02 +0300, Dmitry Osipenko wrote: >> ... >>> Marcel, you previously mentioned that reverting of your DT patch >>> works for the >>> Colibri now. Does that reverting also work for the 4.17 kernel? If >>> yes, I may >>> add stable

Re: [PATCH v1 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers

2018-05-03 Thread Marcel Ziswiler
On Thu, 2018-05-03 at 15:02 +0300, Dmitry Osipenko wrote: > ... > > Marcel, you previously mentioned that reverting of your DT patch > > works for the > > Colibri now. Does that reverting also work for the 4.17 kernel? If > > yes, I may > > add stable tag to the revert-patch to get back paz00 worki

Re: [PATCH v1 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers

2018-05-03 Thread Dmitry Osipenko
On 03.05.2018 14:59, Dmitry Osipenko wrote: > On 27.04.2018 16:00, Marcel Ziswiler wrote: >> On Fri, 2018-04-27 at 15:54 +0300, Dmitry Osipenko wrote: >>> Hi Marcel, >>> >>> On 27.04.2018 15:33, Ziswiler wrote: Hi Dmitry Isn't the CLK_RST_CONTROLLER_MISC_CLK_ENB_0 the other way arou

Re: [PATCH v1 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers

2018-05-03 Thread Dmitry Osipenko
On 27.04.2018 16:00, Marcel Ziswiler wrote: > On Fri, 2018-04-27 at 15:54 +0300, Dmitry Osipenko wrote: >> Hi Marcel, >> >> On 27.04.2018 15:33, Ziswiler wrote: >>> Hi Dmitry >>> >>> Isn't the CLK_RST_CONTROLLER_MISC_CLK_ENB_0 the other way around >>> e.g. >>> DEV1_OSC_DIV_SEL at bit 23:22 and DEV

Re: [PATCH v1 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers

2018-04-30 Thread Peter De Schrijver
On Fri, Apr 27, 2018 at 02:58:15AM +0300, Dmitry Osipenko wrote: > CDEV1/CDEV2 clocks could have corresponding oscillator clock divider as > a parent. Add these dividers in order to be able to provide that parent > option. > > Signed-off-by: Dmitry Osipenko > --- > drivers/clk/tegra/clk-tegra20.

Re: [PATCH v1 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers

2018-04-27 Thread Marcel Ziswiler
On Fri, 2018-04-27 at 15:54 +0300, Dmitry Osipenko wrote: > Hi Marcel, > > On 27.04.2018 15:33, Ziswiler wrote: > > Hi Dmitry > > > > Isn't the CLK_RST_CONTROLLER_MISC_CLK_ENB_0 the other way around > > e.g. > > DEV1_OSC_DIV_SEL at bit 23:22 and DEV2_OSC_DIV_SEL at 21:20? > > > > On Fri, 2018-0

Re: [PATCH v1 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers

2018-04-27 Thread Dmitry Osipenko
Hi Marcel, On 27.04.2018 15:33, Ziswiler wrote: > Hi Dmitry > > Isn't the CLK_RST_CONTROLLER_MISC_CLK_ENB_0 the other way around e.g. > DEV1_OSC_DIV_SEL at bit 23:22 and DEV2_OSC_DIV_SEL at 21:20? > > On Fri, 2018-04-27 at 02:58 +0300, Dmitry Osipenko wrote: >> CDEV1/CDEV2 clocks could have cor

Re: [PATCH v1 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers

2018-04-27 Thread Marcel Ziswiler
Hi Dmitry Isn't the CLK_RST_CONTROLLER_MISC_CLK_ENB_0 the other way around e.g. DEV1_OSC_DIV_SEL at bit 23:22 and DEV2_OSC_DIV_SEL at 21:20? On Fri, 2018-04-27 at 02:58 +0300, Dmitry Osipenko wrote: > CDEV1/CDEV2 clocks could have corresponding oscillator clock divider > as > a parent. Add these

[PATCH v1 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers

2018-04-26 Thread Dmitry Osipenko
CDEV1/CDEV2 clocks could have corresponding oscillator clock divider as a parent. Add these dividers in order to be able to provide that parent option. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/clk