Re: [PATCH v1 2/2] cpufreq: tegra20: Use PLL_C as intermediate clock source

2018-05-25 Thread Dmitry Osipenko
On 25.05.2018 11:36, Rafael J. Wysocki wrote: > On Fri, May 25, 2018 at 10:14 AM, Rafael J. Wysocki wrote: >> On Thu, May 24, 2018 at 2:28 PM, Dmitry Osipenko wrote: >>> On 24.05.2018 11:01, Rafael J. Wysocki wrote: On Thu, May 24, 2018 at 7:37 AM, Dmitry Osipenko wrote: > On 24.05.2018

Re: [PATCH v1 2/2] cpufreq: tegra20: Use PLL_C as intermediate clock source

2018-05-25 Thread Rafael J. Wysocki
On Fri, May 25, 2018 at 10:14 AM, Rafael J. Wysocki wrote: > On Thu, May 24, 2018 at 2:28 PM, Dmitry Osipenko wrote: >> On 24.05.2018 11:01, Rafael J. Wysocki wrote: >>> On Thu, May 24, 2018 at 7:37 AM, Dmitry Osipenko wrote: On 24.05.2018 07:30, Viresh Kumar wrote: > On 23-05-18, 19:00

Re: [PATCH v1 2/2] cpufreq: tegra20: Use PLL_C as intermediate clock source

2018-05-25 Thread Dmitry Osipenko
On 25.05.2018 09:32, Peter De Schrijver wrote: > On Thu, May 24, 2018 at 03:49:22PM +0300, Dmitry Osipenko wrote: >> On 24.05.2018 13:04, Peter De Schrijver wrote: >>> On Wed, May 23, 2018 at 07:00:20PM +0300, Dmitry Osipenko wrote: PLL_C is running at 600MHz which is significantly higher than

Re: [PATCH v1 2/2] cpufreq: tegra20: Use PLL_C as intermediate clock source

2018-05-25 Thread Rafael J. Wysocki
On Thu, May 24, 2018 at 2:28 PM, Dmitry Osipenko wrote: > On 24.05.2018 11:01, Rafael J. Wysocki wrote: >> On Thu, May 24, 2018 at 7:37 AM, Dmitry Osipenko wrote: >>> On 24.05.2018 07:30, Viresh Kumar wrote: On 23-05-18, 19:00, Dmitry Osipenko wrote: > PLL_C is running at 600MHz which is

Re: [PATCH v1 2/2] cpufreq: tegra20: Use PLL_C as intermediate clock source

2018-05-24 Thread Peter De Schrijver
On Thu, May 24, 2018 at 03:49:22PM +0300, Dmitry Osipenko wrote: > On 24.05.2018 13:04, Peter De Schrijver wrote: > > On Wed, May 23, 2018 at 07:00:20PM +0300, Dmitry Osipenko wrote: > >> PLL_C is running at 600MHz which is significantly higher than the 216MHz > >> of the PLL_P and it is known that

Re: [PATCH v1 2/2] cpufreq: tegra20: Use PLL_C as intermediate clock source

2018-05-24 Thread Dmitry Osipenko
On 24.05.2018 13:04, Peter De Schrijver wrote: > On Wed, May 23, 2018 at 07:00:20PM +0300, Dmitry Osipenko wrote: >> PLL_C is running at 600MHz which is significantly higher than the 216MHz >> of the PLL_P and it is known that PLL_C is always-ON because AHB BUS is >> running on that PLL. Let's use

Re: [PATCH v1 2/2] cpufreq: tegra20: Use PLL_C as intermediate clock source

2018-05-24 Thread Dmitry Osipenko
On 24.05.2018 11:01, Rafael J. Wysocki wrote: > On Thu, May 24, 2018 at 7:37 AM, Dmitry Osipenko wrote: >> On 24.05.2018 07:30, Viresh Kumar wrote: >>> On 23-05-18, 19:00, Dmitry Osipenko wrote: PLL_C is running at 600MHz which is significantly higher than the 216MHz of the PLL_P and it

Re: [PATCH v1 2/2] cpufreq: tegra20: Use PLL_C as intermediate clock source

2018-05-24 Thread Peter De Schrijver
On Wed, May 23, 2018 at 07:00:20PM +0300, Dmitry Osipenko wrote: > PLL_C is running at 600MHz which is significantly higher than the 216MHz > of the PLL_P and it is known that PLL_C is always-ON because AHB BUS is > running on that PLL. Let's use PLL_C as intermediate clock source, making > CPU sna

Re: [PATCH v1 2/2] cpufreq: tegra20: Use PLL_C as intermediate clock source

2018-05-24 Thread Rafael J. Wysocki
On Thu, May 24, 2018 at 7:37 AM, Dmitry Osipenko wrote: > On 24.05.2018 07:30, Viresh Kumar wrote: >> On 23-05-18, 19:00, Dmitry Osipenko wrote: >>> PLL_C is running at 600MHz which is significantly higher than the 216MHz >>> of the PLL_P and it is known that PLL_C is always-ON because AHB BUS is

Re: [PATCH v1 2/2] cpufreq: tegra20: Use PLL_C as intermediate clock source

2018-05-23 Thread Dmitry Osipenko
On 24.05.2018 07:30, Viresh Kumar wrote: > On 23-05-18, 19:00, Dmitry Osipenko wrote: >> PLL_C is running at 600MHz which is significantly higher than the 216MHz >> of the PLL_P and it is known that PLL_C is always-ON because AHB BUS is >> running on that PLL. Let's use PLL_C as intermediate clock

Re: [PATCH v1 2/2] cpufreq: tegra20: Use PLL_C as intermediate clock source

2018-05-23 Thread Viresh Kumar
On 23-05-18, 19:00, Dmitry Osipenko wrote: > PLL_C is running at 600MHz which is significantly higher than the 216MHz > of the PLL_P and it is known that PLL_C is always-ON because AHB BUS is > running on that PLL. Let's use PLL_C as intermediate clock source, making > CPU snappier a tad during of

[PATCH v1 2/2] cpufreq: tegra20: Use PLL_C as intermediate clock source

2018-05-23 Thread Dmitry Osipenko
PLL_C is running at 600MHz which is significantly higher than the 216MHz of the PLL_P and it is known that PLL_C is always-ON because AHB BUS is running on that PLL. Let's use PLL_C as intermediate clock source, making CPU snappier a tad during of the frequency transition. Signed-off-by: Dmitry Os