Re: [PATCH v1 2/5] clk: tegra: Bump SCLK clock rate to 216MHz on Tegra20

2017-09-26 Thread Peter De Schrijver
On Tue, Sep 26, 2017 at 02:22:03AM +0300, Dmitry Osipenko wrote: > AHB DMA is a running on 1/2 of SCLK rate, APB on 1/4. Increasing SCLK rate > results in an increased DMA transfer rate. > > Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver

Re: [PATCH v1 2/5] clk: tegra: Bump SCLK clock rate to 216MHz on Tegra20

2017-09-26 Thread Peter De Schrijver
On Tue, Sep 26, 2017 at 02:22:03AM +0300, Dmitry Osipenko wrote: > AHB DMA is a running on 1/2 of SCLK rate, APB on 1/4. Increasing SCLK rate > results in an increased DMA transfer rate. > > Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver > --- > drivers/clk/tegra/clk-tegra20.c |

[PATCH v1 2/5] clk: tegra: Bump SCLK clock rate to 216MHz on Tegra20

2017-09-25 Thread Dmitry Osipenko
AHB DMA is a running on 1/2 of SCLK rate, APB on 1/4. Increasing SCLK rate results in an increased DMA transfer rate. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH v1 2/5] clk: tegra: Bump SCLK clock rate to 216MHz on Tegra20

2017-09-25 Thread Dmitry Osipenko
AHB DMA is a running on 1/2 of SCLK rate, APB on 1/4. Increasing SCLK rate results in an increased DMA transfer rate. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra20.c