On Mon, Dec 07, 2020 at 04:02:15PM -0800, Sowjanya Komatineni wrote:
> So by having it in spi_message, controller driver can get dummy cycles info
> a head of transfers so it can program this along with address bytes transfer
> phase.
That sounds fine.
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On Mon, Dec 07, 2020 at 04:14:53PM -0800, Sowjanya Komatineni wrote:
> On 12/6/20 10:16 AM, Lukas Wunner wrote:
> > However, be sure to use the devm variant to *allocate* the SPI controller,
> > i.e. use devm_spi_alloc_master() instead of spi_alloc_master().
>
> Thanks Lukas. I see
On 12/6/20 10:16 AM, Lukas Wunner wrote:
On Tue, Dec 01, 2020 at 01:12:44PM -0800, Sowjanya Komatineni wrote:
+ ret = devm_spi_register_master(>dev, master);
[...]
+static int tegra_qspi_remove(struct platform_device *pdev)
+{
+ struct spi_master *master =
On Tue, Dec 01, 2020 at 01:12:44PM -0800, Sowjanya Komatineni wrote:
> + ret = devm_spi_register_master(>dev, master);
[...]
> +static int tegra_qspi_remove(struct platform_device *pdev)
> +{
> + struct spi_master *master = platform_get_drvdata(pdev);
> + struct tegra_qspi_data *tqspi
On 12/4/20 2:46 PM, Mark Brown wrote:
On Fri, Dec 04, 2020 at 01:04:46PM -0800, Sowjanya Komatineni wrote:
On 12/4/20 10:52 AM, Mark Brown wrote:
On Thu, Dec 03, 2020 at 04:22:54PM -0800, Sowjanya Komatineni wrote:
Also unpack mode needs to manually put the bytes together from read data to
On Fri, Dec 04, 2020 at 01:04:46PM -0800, Sowjanya Komatineni wrote:
> On 12/4/20 10:52 AM, Mark Brown wrote:
> > On Thu, Dec 03, 2020 at 04:22:54PM -0800, Sowjanya Komatineni wrote:
> > > Also unpack mode needs to manually put the bytes together from read data
> > > to
> > > SPI core rx buffer.
Thanks Thierry. Will address below suggestions in v2.
Some inline comments below regarding client data part of controller driver.
Regards,
Sowjanya
On 12/4/20 4:11 AM, Thierry Reding wrote:
On Tue, Dec 01, 2020 at 01:12:44PM -0800, Sowjanya Komatineni wrote:
Tegra SoC has a Quad SPI
Thanks Jon. Will address below suggestions in v2.
Regards,
Sowjanya
On 12/4/20 6:41 AM, Jon Hunter wrote:
On 01/12/2020 21:12, Sowjanya Komatineni wrote:
Tegra SoC has a Quad SPI controller starting from Tegra210.
This patch adds support for Tegra210 QSPI controller.
Signed-off-by:
On 12/4/20 10:52 AM, Mark Brown wrote:
On Thu, Dec 03, 2020 at 04:22:54PM -0800, Sowjanya Komatineni wrote:
On 12/2/20 11:17 AM, Sowjanya Komatineni wrote:
It seems weird that this device needs us to do a memcpy() to do DMA,
most devices are able to DMA directly from the buffers provided by
On Thu, Dec 03, 2020 at 04:22:54PM -0800, Sowjanya Komatineni wrote:
> On 12/2/20 11:17 AM, Sowjanya Komatineni wrote:
> > > It seems weird that this device needs us to do a memcpy() to do DMA,
> > > most devices are able to DMA directly from the buffers provided by the
> > > SPI API (and let the
On 01/12/2020 21:12, Sowjanya Komatineni wrote:
> Tegra SoC has a Quad SPI controller starting from Tegra210.
>
> This patch adds support for Tegra210 QSPI controller.
>
> Signed-off-by: Sowjanya Komatineni
> ---
> drivers/spi/Kconfig |9 +
> drivers/spi/Makefile |1 +
>
On Wed, Dec 02, 2020 at 11:17:18AM -0800, Sowjanya Komatineni wrote:
> On 12/2/20 9:27 AM, Mark Brown wrote:
> > On Tue, Dec 01, 2020 at 01:12:44PM -0800, Sowjanya Komatineni wrote:
[...]
> > > +static int tegra_qspi_setup(struct spi_device *spi)
> > > +{
> > > + if (cdata &&
On Wed, Dec 02, 2020 at 05:27:21PM +, Mark Brown wrote:
> On Tue, Dec 01, 2020 at 01:12:44PM -0800, Sowjanya Komatineni wrote:
> > Tegra SoC has a Quad SPI controller starting from Tegra210.
> >
> > This patch adds support for Tegra210 QSPI controller.
>
> This looks pretty clean but I've
On Tue, Dec 01, 2020 at 01:12:44PM -0800, Sowjanya Komatineni wrote:
> Tegra SoC has a Quad SPI controller starting from Tegra210.
>
> This patch adds support for Tegra210 QSPI controller.
>
> Signed-off-by: Sowjanya Komatineni
> ---
> drivers/spi/Kconfig |9 +
> drivers/spi/Makefile
On 12/2/20 11:17 AM, Sowjanya Komatineni wrote:
On 12/2/20 9:27 AM, Mark Brown wrote:
On Tue, Dec 01, 2020 at 01:12:44PM -0800, Sowjanya Komatineni wrote:
Tegra SoC has a Quad SPI controller starting from Tegra210.
This patch adds support for Tegra210 QSPI controller.
This looks pretty
On 12/2/20 9:27 AM, Mark Brown wrote:
On Tue, Dec 01, 2020 at 01:12:44PM -0800, Sowjanya Komatineni wrote:
Tegra SoC has a Quad SPI controller starting from Tegra210.
This patch adds support for Tegra210 QSPI controller.
This looks pretty clean but I've got a few questions below about how
On Tue, Dec 01, 2020 at 01:12:44PM -0800, Sowjanya Komatineni wrote:
> Tegra SoC has a Quad SPI controller starting from Tegra210.
>
> This patch adds support for Tegra210 QSPI controller.
This looks pretty clean but I've got a few questions below about how
this integrates with the frameworks as
Hi Sowjanya,
I love your patch! Perhaps something to improve:
[auto build test WARNING on spi/for-next]
[also build test WARNING on robh/for-next tegra/for-next v5.10-rc6
next-20201201]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest
Tegra SoC has a Quad SPI controller starting from Tegra210.
This patch adds support for Tegra210 QSPI controller.
Signed-off-by: Sowjanya Komatineni
---
drivers/spi/Kconfig |9 +
drivers/spi/Makefile |1 +
drivers/spi/qspi-tegra.c | 1418
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