On 28.09.2017 19:22, Vinod Koul wrote:
> On Thu, Sep 28, 2017 at 05:35:59PM +0300, Dmitry Osipenko wrote:
>> On 28.09.2017 17:06, Dmitry Osipenko wrote:
>>> On 28.09.2017 12:29, Vinod Koul wrote:
> + default:
> + return -EINVAL;
> + }
> +
> + ahb_seq = burst <<
On 28.09.2017 19:22, Vinod Koul wrote:
> On Thu, Sep 28, 2017 at 05:35:59PM +0300, Dmitry Osipenko wrote:
>> On 28.09.2017 17:06, Dmitry Osipenko wrote:
>>> On 28.09.2017 12:29, Vinod Koul wrote:
> + default:
> + return -EINVAL;
> + }
> +
> + ahb_seq = burst <<
On Thu, Sep 28, 2017 at 05:35:59PM +0300, Dmitry Osipenko wrote:
> On 28.09.2017 17:06, Dmitry Osipenko wrote:
> > On 28.09.2017 12:29, Vinod Koul wrote:
> >>> + default:
> >>> + return -EINVAL;
> >>> + }
> >>> +
> >>> + ahb_seq = burst << TEGRA_AHBDMA_CHANNEL_AHB_BURST_SHIFT;
> >>> +
On Thu, Sep 28, 2017 at 05:35:59PM +0300, Dmitry Osipenko wrote:
> On 28.09.2017 17:06, Dmitry Osipenko wrote:
> > On 28.09.2017 12:29, Vinod Koul wrote:
> >>> + default:
> >>> + return -EINVAL;
> >>> + }
> >>> +
> >>> + ahb_seq = burst << TEGRA_AHBDMA_CHANNEL_AHB_BURST_SHIFT;
> >>> +
On Thu, Sep 28, 2017 at 05:06:03PM +0300, Dmitry Osipenko wrote:
> On 28.09.2017 12:29, Vinod Koul wrote:
> >> + default:
> >> + return -EINVAL;
> >> + }
> >> +
> >> + ahb_seq = burst << TEGRA_AHBDMA_CHANNEL_AHB_BURST_SHIFT;
> >> + ahb_seq |= TEGRA_AHBDMA_CHANNEL_ADDR_WRAP;
> >> +
On Thu, Sep 28, 2017 at 05:06:03PM +0300, Dmitry Osipenko wrote:
> On 28.09.2017 12:29, Vinod Koul wrote:
> >> + default:
> >> + return -EINVAL;
> >> + }
> >> +
> >> + ahb_seq = burst << TEGRA_AHBDMA_CHANNEL_AHB_BURST_SHIFT;
> >> + ahb_seq |= TEGRA_AHBDMA_CHANNEL_ADDR_WRAP;
> >> +
On 28.09.2017 17:06, Dmitry Osipenko wrote:
> On 28.09.2017 12:29, Vinod Koul wrote:
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +
>>> + ahb_seq = burst << TEGRA_AHBDMA_CHANNEL_AHB_BURST_SHIFT;
>>> + ahb_seq |= TEGRA_AHBDMA_CHANNEL_ADDR_WRAP;
>>> + ahb_seq |=
On 28.09.2017 17:06, Dmitry Osipenko wrote:
> On 28.09.2017 12:29, Vinod Koul wrote:
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +
>>> + ahb_seq = burst << TEGRA_AHBDMA_CHANNEL_AHB_BURST_SHIFT;
>>> + ahb_seq |= TEGRA_AHBDMA_CHANNEL_ADDR_WRAP;
>>> + ahb_seq |=
On 28.09.2017 12:29, Vinod Koul wrote:
>> +default:
>> +return -EINVAL;
>> +}
>> +
>> +ahb_seq = burst << TEGRA_AHBDMA_CHANNEL_AHB_BURST_SHIFT;
>> +ahb_seq |= TEGRA_AHBDMA_CHANNEL_ADDR_WRAP;
>> +ahb_seq |= TEGRA_AHBDMA_CHANNEL_INTR_ENB;
>> +
>> +
On 28.09.2017 12:29, Vinod Koul wrote:
>> +default:
>> +return -EINVAL;
>> +}
>> +
>> +ahb_seq = burst << TEGRA_AHBDMA_CHANNEL_AHB_BURST_SHIFT;
>> +ahb_seq |= TEGRA_AHBDMA_CHANNEL_ADDR_WRAP;
>> +ahb_seq |= TEGRA_AHBDMA_CHANNEL_INTR_ENB;
>> +
>> +
On 28.09.2017 12:29, Vinod Koul wrote:
> On Tue, Sep 26, 2017 at 02:22:05AM +0300, Dmitry Osipenko wrote:
>
>> +config TEGRA20_AHB_DMA
>> +tristate "NVIDIA Tegra20 AHB DMA support"
>> +depends on ARCH_TEGRA
>
> Can we add COMPILE_TEST, helps me compile drivers
>
Good point.
>>
On 28.09.2017 12:29, Vinod Koul wrote:
> On Tue, Sep 26, 2017 at 02:22:05AM +0300, Dmitry Osipenko wrote:
>
>> +config TEGRA20_AHB_DMA
>> +tristate "NVIDIA Tegra20 AHB DMA support"
>> +depends on ARCH_TEGRA
>
> Can we add COMPILE_TEST, helps me compile drivers
>
Good point.
>>
On Tue, Sep 26, 2017 at 02:22:05AM +0300, Dmitry Osipenko wrote:
> +config TEGRA20_AHB_DMA
> + tristate "NVIDIA Tegra20 AHB DMA support"
> + depends on ARCH_TEGRA
Can we add COMPILE_TEST, helps me compile drivers
> +#include
> +#include
> +#include
> +#include
> +#include
>
On Tue, Sep 26, 2017 at 02:22:05AM +0300, Dmitry Osipenko wrote:
> +config TEGRA20_AHB_DMA
> + tristate "NVIDIA Tegra20 AHB DMA support"
> + depends on ARCH_TEGRA
Can we add COMPILE_TEST, helps me compile drivers
> +#include
> +#include
> +#include
> +#include
> +#include
>
On 27.09.2017 00:37, Jon Hunter wrote:
> Hi Dmitry,
>
> On 26/09/17 17:06, Dmitry Osipenko wrote:
>> Hi Jon,
>>
>> On 26.09.2017 17:45, Jon Hunter wrote:
>>> Hi Dmitry,
>>>
>>> On 26/09/17 00:22, Dmitry Osipenko wrote:
AHB DMA controller presents on Tegra20/30 SoC's, it supports transfers
On 27.09.2017 00:37, Jon Hunter wrote:
> Hi Dmitry,
>
> On 26/09/17 17:06, Dmitry Osipenko wrote:
>> Hi Jon,
>>
>> On 26.09.2017 17:45, Jon Hunter wrote:
>>> Hi Dmitry,
>>>
>>> On 26/09/17 00:22, Dmitry Osipenko wrote:
AHB DMA controller presents on Tegra20/30 SoC's, it supports transfers
Hi Dmitry,
On 26/09/17 17:06, Dmitry Osipenko wrote:
> Hi Jon,
>
> On 26.09.2017 17:45, Jon Hunter wrote:
>> Hi Dmitry,
>>
>> On 26/09/17 00:22, Dmitry Osipenko wrote:
>>> AHB DMA controller presents on Tegra20/30 SoC's, it supports transfers
>>> memory <-> AHB bus peripherals as well as
Hi Dmitry,
On 26/09/17 17:06, Dmitry Osipenko wrote:
> Hi Jon,
>
> On 26.09.2017 17:45, Jon Hunter wrote:
>> Hi Dmitry,
>>
>> On 26/09/17 00:22, Dmitry Osipenko wrote:
>>> AHB DMA controller presents on Tegra20/30 SoC's, it supports transfers
>>> memory <-> AHB bus peripherals as well as
Hi Jon,
On 26.09.2017 17:45, Jon Hunter wrote:
> Hi Dmitry,
>
> On 26/09/17 00:22, Dmitry Osipenko wrote:
>> AHB DMA controller presents on Tegra20/30 SoC's, it supports transfers
>> memory <-> AHB bus peripherals as well as mem-to-mem transfers. Driver
>> doesn't yet implement transfers larger
Hi Jon,
On 26.09.2017 17:45, Jon Hunter wrote:
> Hi Dmitry,
>
> On 26/09/17 00:22, Dmitry Osipenko wrote:
>> AHB DMA controller presents on Tegra20/30 SoC's, it supports transfers
>> memory <-> AHB bus peripherals as well as mem-to-mem transfers. Driver
>> doesn't yet implement transfers larger
Hi Dmitry,
On 26/09/17 00:22, Dmitry Osipenko wrote:
> AHB DMA controller presents on Tegra20/30 SoC's, it supports transfers
> memory <-> AHB bus peripherals as well as mem-to-mem transfers. Driver
> doesn't yet implement transfers larger than 64K and scatter-gather
> transfers that have NENT >
Hi Dmitry,
On 26/09/17 00:22, Dmitry Osipenko wrote:
> AHB DMA controller presents on Tegra20/30 SoC's, it supports transfers
> memory <-> AHB bus peripherals as well as mem-to-mem transfers. Driver
> doesn't yet implement transfers larger than 64K and scatter-gather
> transfers that have NENT >
AHB DMA controller presents on Tegra20/30 SoC's, it supports transfers
memory <-> AHB bus peripherals as well as mem-to-mem transfers. Driver
doesn't yet implement transfers larger than 64K and scatter-gather
transfers that have NENT > 1, HW doesn't have native support for these
cases.
AHB DMA controller presents on Tegra20/30 SoC's, it supports transfers
memory <-> AHB bus peripherals as well as mem-to-mem transfers. Driver
doesn't yet implement transfers larger than 64K and scatter-gather
transfers that have NENT > 1, HW doesn't have native support for these
cases.
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