Hi Boris,
On 04/01/16 11:47, Boris Brezillon wrote:
Hi Harvey,
On Mon, 4 Jan 2016 10:24:15 +
Harvey Hunt wrote:
+
+static void jz4780_bch_disable(struct jz4780_bch *bch)
+{
+ writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);
+ writel(BCH_BHCR_BCHE, bch->base + BCH
Hi Harvey,
On Mon, 4 Jan 2016 10:24:15 +
Harvey Hunt wrote:
> >> +
> >> +static void jz4780_bch_disable(struct jz4780_bch *bch)
> >> +{
> >> + writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);
> >> + writel(BCH_BHCR_BCHE, bch->base + BCH_BHCCR);
> >
> > Not sure what BCH_BHCR_B
Hi Boris,
Happy New Year.
Thanks for the comments - I'll send out a new patchset today.
On 28/12/15 08:25, Boris Brezillon wrote:
Hi Harvey,
I found a few remaining issues. Once fixed you can add my
Reviewed-by: Boris Brezillon
On Thu, 24 Dec 2015 12:20:14 +
Harvey Hunt wrote:
From:
Hi Harvey,
I found a few remaining issues. Once fixed you can add my
Reviewed-by: Boris Brezillon
On Thu, 24 Dec 2015 12:20:14 +
Harvey Hunt wrote:
> From: Alex Smith
>
> Add a driver for NAND devices connected to the NEMC on JZ4780 SoCs, as
> well as the hardware BCH controller. DMA is
From: Alex Smith
Add a driver for NAND devices connected to the NEMC on JZ4780 SoCs, as
well as the hardware BCH controller. DMA is not currently implemented.
While older 47xx SoCs also have a BCH controller, they are incompatible
with the one in the 4780 due to differing register/bit positions,
5 matches
Mail list logo