Re: [PATCH v10 3/6] clk: qcom: Add A53 PLL support

2017-12-04 Thread Bjorn Andersson
On Fri 01 Dec 09:02 PST 2017, Georgi Djakov wrote: > The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, > a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources > are connected to a mux and half-integer divider, which is feeding the > CPU cores. > > This patch

Re: [PATCH v10 3/6] clk: qcom: Add A53 PLL support

2017-12-04 Thread Bjorn Andersson
On Fri 01 Dec 09:02 PST 2017, Georgi Djakov wrote: > The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, > a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources > are connected to a mux and half-integer divider, which is feeding the > CPU cores. > > This patch

[PATCH v10 3/6] clk: qcom: Add A53 PLL support

2017-12-01 Thread Georgi Djakov
The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources are connected to a mux and half-integer divider, which is feeding the CPU cores. This patch adds support for the primary CPU PLL which generates the higher

[PATCH v10 3/6] clk: qcom: Add A53 PLL support

2017-12-01 Thread Georgi Djakov
The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources are connected to a mux and half-integer divider, which is feeding the CPU cores. This patch adds support for the primary CPU PLL which generates the higher