On Fri 01 Dec 09:02 PST 2017, Georgi Djakov wrote:
> Update the binding documentation for APCS to mention that the APCS
> hardware block also expose a clock controller functionality.
>
> The APCS clock controller is a mux and half-integer divider. It has the
> main CPU PLL as an input and provide
On Fri, Dec 01, 2017 at 07:02:23PM +0200, Georgi Djakov wrote:
> Update the binding documentation for APCS to mention that the APCS
> hardware block also expose a clock controller functionality.
>
> The APCS clock controller is a mux and half-integer divider. It has the
> main CPU PLL as an input
Update the binding documentation for APCS to mention that the APCS
hardware block also expose a clock controller functionality.
The APCS clock controller is a mux and half-integer divider. It has the
main CPU PLL as an input and provides the clock for the application CPU.
Signed-off-by: Georgi Dj
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