Re: [PATCH v10 6/6] clk: qcom: Add APCS clock controller support

2017-12-05 Thread Georgi Djakov
On 12/05/2017 08:01 AM, Bjorn Andersson wrote: > On Fri 01 Dec 09:02 PST 2017, Georgi Djakov wrote: > [..] >> diff --git a/drivers/clk/qcom/apcs-msm8916.c >> b/drivers/clk/qcom/apcs-msm8916.c >> new file mode 100644 >> index ..f71039ff2347 >> --- /dev/null >> +++

Re: [PATCH v10 6/6] clk: qcom: Add APCS clock controller support

2017-12-05 Thread Georgi Djakov
On 12/05/2017 08:01 AM, Bjorn Andersson wrote: > On Fri 01 Dec 09:02 PST 2017, Georgi Djakov wrote: > [..] >> diff --git a/drivers/clk/qcom/apcs-msm8916.c >> b/drivers/clk/qcom/apcs-msm8916.c >> new file mode 100644 >> index ..f71039ff2347 >> --- /dev/null >> +++

Re: [PATCH v10 6/6] clk: qcom: Add APCS clock controller support

2017-12-04 Thread Bjorn Andersson
On Fri 01 Dec 09:02 PST 2017, Georgi Djakov wrote: [..] > diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c > new file mode 100644 > index ..f71039ff2347 > --- /dev/null > +++ b/drivers/clk/qcom/apcs-msm8916.c > @@ -0,0 +1,149 @@ > +/* > + * Qualcomm APCS

Re: [PATCH v10 6/6] clk: qcom: Add APCS clock controller support

2017-12-04 Thread Bjorn Andersson
On Fri 01 Dec 09:02 PST 2017, Georgi Djakov wrote: [..] > diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c > new file mode 100644 > index ..f71039ff2347 > --- /dev/null > +++ b/drivers/clk/qcom/apcs-msm8916.c > @@ -0,0 +1,149 @@ > +/* > + * Qualcomm APCS

[PATCH v10 6/6] clk: qcom: Add APCS clock controller support

2017-12-01 Thread Georgi Djakov
Add a driver for the APCS clock controller. It is part of the APCS hardware block, which among other things implements also a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the dedicated APCS (A53) PLL. The source and the divider can be set both at

[PATCH v10 6/6] clk: qcom: Add APCS clock controller support

2017-12-01 Thread Georgi Djakov
Add a driver for the APCS clock controller. It is part of the APCS hardware block, which among other things implements also a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the dedicated APCS (A53) PLL. The source and the divider can be set both at