> Ping
>
> > Subject: RE: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for
> > Xilinx NWL PCIe Host Controller
> >
> > > On Mon, Dec 21, 2015 at 05:23:47AM +, Bharat Kumar Gogada wrote:
> > > > Hi Bjorn, can you com
> Ping
>
> > Subject: RE: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for
> > Xilinx NWL PCIe Host Controller
> >
> > > On Mon, Dec 21, 2015 at 05:23:47AM +, Bharat Kumar Gogada wrote:
> > > > Hi Bjorn, can you com
Ping
> Subject: RE: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
>
> > On Mon, Dec 21, 2015 at 05:23:47AM +, Bharat Kumar Gogada wrote:
> > > Hi Bjorn, can you comment on this. Marc has also replied for query
> >
Ping
> Subject: RE: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
>
> > On Mon, Dec 21, 2015 at 05:23:47AM +, Bharat Kumar Gogada wrote:
> > > Hi Bjorn, can you comment on this. Marc has also replied for query
> >
Hi Bjorn, can you comment on this. Marc has also replied for query on
irq_dispose_mapping().
> > Subject: RE: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for
> > Xilinx NWL PCIe Host Controller
> >
> > > Subject: Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added suppor
Hi Bjorn, can you comment on this. Marc has also replied for query on
irq_dispose_mapping().
> > Subject: RE: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for
> > Xilinx NWL PCIe Host Controller
> >
> > > Subject: Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added suppor
Hi Bjorn, can you comment on this. Marc has also replied for query on
irq_dispose_mapping().
> Subject: RE: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
>
> > Subject: Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for
> >
Hi Bjorn, can you comment on this. Marc has also replied for query on
irq_dispose_mapping().
> Subject: RE: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
>
> > Subject: Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for
> >
On 10/12/15 20:18, Bjorn Helgaas wrote:
> [+cc Marc for irq_dispose_mapping() question]
+ }
+ } while (status);
+
+ return retval;
+ for (i = 0; i < 4; i++) {
+ irq = irq_find_mapping(pcie->legacy_irq_domain, i + 1);
+ if (irq
On 10/12/15 20:18, Bjorn Helgaas wrote:
> [+cc Marc for irq_dispose_mapping() question]
+ }
+ } while (status);
+
+ return retval;
+ for (i = 0; i < 4; i++) {
+ irq = irq_find_mapping(pcie->legacy_irq_domain, i + 1);
+ if (irq
On 10.12.2015 18:25, Bjorn Helgaas wrote:
> On Thu, Dec 10, 2015 at 08:02:05AM +0100, Michal Simek wrote:
>> Hi Bjorn,
>>
>> On 10.12.2015 00:19, Bjorn Helgaas wrote:
>>> [+cc Michal, Paul, Thierry, Stephen, Alexandre (see irq_dispose_mapping
>>> questions below)]
>>>
>>> On Sun, Nov 29, 2015 at
> Subject: Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
>
> [+cc Marc for irq_dispose_mapping() question]
>
> On Thu, Dec 10, 2015 at 02:10:34PM +, Bharat Kumar Gogada wrote:
> I'm trying to figure out what the difference
[+cc Marc for irq_dispose_mapping() question]
On Thu, Dec 10, 2015 at 02:10:34PM +, Bharat Kumar Gogada wrote:
> > Subject: Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> > > +static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int
> > > +devfn) {
> > > +
On Thu, Dec 10, 2015 at 08:02:05AM +0100, Michal Simek wrote:
> Hi Bjorn,
>
> On 10.12.2015 00:19, Bjorn Helgaas wrote:
> > [+cc Michal, Paul, Thierry, Stephen, Alexandre (see irq_dispose_mapping
> > questions below)]
> >
> > On Sun, Nov 29, 2015 at 05:33:53PM +0530, Bharat Kumar Gogada wrote:
> Subject: Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
> > +
> It's a bit sloppy here to return 0, 1, or -EINVAL from a function declared to
> return "bool". A bool function should return "true" or "fals
[+cc Marc for irq_dispose_mapping() question]
On Thu, Dec 10, 2015 at 02:10:34PM +, Bharat Kumar Gogada wrote:
> > Subject: Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> > > +static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int
> > > +devfn) {
> > > +
On Thu, Dec 10, 2015 at 08:02:05AM +0100, Michal Simek wrote:
> Hi Bjorn,
>
> On 10.12.2015 00:19, Bjorn Helgaas wrote:
> > [+cc Michal, Paul, Thierry, Stephen, Alexandre (see irq_dispose_mapping
> > questions below)]
> >
> > On Sun, Nov 29, 2015 at 05:33:53PM +0530, Bharat Kumar Gogada wrote:
> Subject: Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
> > +
> It's a bit sloppy here to return 0, 1, or -EINVAL from a function declared to
> return "bool". A bool function should return "true" or "fals
On 10.12.2015 18:25, Bjorn Helgaas wrote:
> On Thu, Dec 10, 2015 at 08:02:05AM +0100, Michal Simek wrote:
>> Hi Bjorn,
>>
>> On 10.12.2015 00:19, Bjorn Helgaas wrote:
>>> [+cc Michal, Paul, Thierry, Stephen, Alexandre (see irq_dispose_mapping
>>> questions below)]
>>>
>>> On Sun, Nov 29, 2015 at
> Subject: Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
>
> [+cc Marc for irq_dispose_mapping() question]
>
> On Thu, Dec 10, 2015 at 02:10:34PM +, Bharat Kumar Gogada wrote:
> I'm trying to figure out what the difference
Hi Bjorn,
On 10.12.2015 00:19, Bjorn Helgaas wrote:
> [+cc Michal, Paul, Thierry, Stephen, Alexandre (see irq_dispose_mapping
> questions below)]
>
> On Sun, Nov 29, 2015 at 05:33:53PM +0530, Bharat Kumar Gogada wrote:
>> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>>
>>
[+cc Michal, Paul, Thierry, Stephen, Alexandre (see irq_dispose_mapping
questions below)]
On Sun, Nov 29, 2015 at 05:33:53PM +0530, Bharat Kumar Gogada wrote:
> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>
> Signed-off-by: Bharat Kumar Gogada
> Signed-off-by: Ravi Kiran
[+cc Michal, Paul, Thierry, Stephen, Alexandre (see irq_dispose_mapping
questions below)]
On Sun, Nov 29, 2015 at 05:33:53PM +0530, Bharat Kumar Gogada wrote:
> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>
> Signed-off-by: Bharat Kumar Gogada
>
Hi Bjorn,
On 10.12.2015 00:19, Bjorn Helgaas wrote:
> [+cc Michal, Paul, Thierry, Stephen, Alexandre (see irq_dispose_mapping
> questions below)]
>
> On Sun, Nov 29, 2015 at 05:33:53PM +0530, Bharat Kumar Gogada wrote:
>> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>>
>>
On 29/11/15 12:03, Bharat Kumar Gogada wrote:
> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>
> Signed-off-by: Bharat Kumar Gogada
> Signed-off-by: Ravi Kiran Gummaluri
> Acked-by: Rob Herring
I don't have much to add to this, so FWIW:
Reviewed-by: Marc Zyngier
M.
On 29/11/15 12:03, Bharat Kumar Gogada wrote:
> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>
> Signed-off-by: Bharat Kumar Gogada
> Signed-off-by: Ravi Kiran Gummaluri
> Acked-by: Rob Herring
I don't have much to add
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
Signed-off-by: Bharat Kumar Gogada
Signed-off-by: Ravi Kiran Gummaluri
Acked-by: Rob Herring
---
Changes for v11:
-> Changed data types of bridge, pcie controller and ecam base address
-> Added programming of E_BREG_BASE_HI,
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
Signed-off-by: Bharat Kumar Gogada
Signed-off-by: Ravi Kiran Gummaluri
Acked-by: Rob Herring
---
Changes for v11:
-> Changed data types of bridge, pcie controller and ecam base
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