>
> This last define is not used anywhere. I told you before, but addressing my
> review comments completely is an unduly burden, or what?
>
I left to be consistent with the rest of the file. I will remove the line.
>
> This last define is not used anywhere. I told you before, but addressing my
> review comments completely is an unduly burden, or what?
>
I left to be consistent with the rest of the file. I will remove the line.
On Tue, 20 Dec 2016, Grzegorz Andrejczuk wrote:
>
> diff --git a/arch/x86/include/asm/msr-index.h
> b/arch/x86/include/asm/msr-index.h
> index 78f3760..55ffae0 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -539,6 +539,12 @@
> #define
On Tue, 20 Dec 2016, Grzegorz Andrejczuk wrote:
>
> diff --git a/arch/x86/include/asm/msr-index.h
> b/arch/x86/include/asm/msr-index.h
> index 78f3760..55ffae0 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -539,6 +539,12 @@
> #define
Define new MSR MISC_FEATURE_ENABLES (0x140).
On supported CPUs if bit 1 of this new register is set,
then calling MONITOR and MWAIT instructions outside of ring 0 will
not cause invalid-opcode exception.
The MSR MISC_FEATURE_ENABLES is not yet documented in the SDM. Here is
the relevant
Define new MSR MISC_FEATURE_ENABLES (0x140).
On supported CPUs if bit 1 of this new register is set,
then calling MONITOR and MWAIT instructions outside of ring 0 will
not cause invalid-opcode exception.
The MSR MISC_FEATURE_ENABLES is not yet documented in the SDM. Here is
the relevant
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