Re: [PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

On Fri, 5 Apr 2024 00:07:06 + "Ho-Ren (Jack) Chuang" wrote: > The current implementation treats emulated memory devices, such as > CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory > (E820_TYPE_RAM). However, these emulated devices have different > characteristics

Re: [External] Re: [PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

On Wed, Apr 10, 2024 at 9:51 AM Jonathan Cameron wrote: > > On Tue, 9 Apr 2024 12:02:31 -0700 > "Ho-Ren (Jack) Chuang" wrote: > > > Hi Jonathan, > > > > On Tue, Apr 9, 2024 at 9:12 AM Jonathan Cameron > > wrote: > > > > > > On Fri, 5 Apr 2024 15:43:47 -0700 > > > "Ho-Ren (Jack) Chuang" wrote:

Re: [External] Re: [PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

On Tue, 9 Apr 2024 12:02:31 -0700 "Ho-Ren (Jack) Chuang" wrote: > Hi Jonathan, > > On Tue, Apr 9, 2024 at 9:12 AM Jonathan Cameron > wrote: > > > > On Fri, 5 Apr 2024 15:43:47 -0700 > > "Ho-Ren (Jack) Chuang" wrote: > > > > > On Fri, Apr 5, 2024 at 7:03 AM Jonathan Cameron > > > wrote: >

Re: [External] Re: [PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

On Tue, Apr 9, 2024 at 7:33 PM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > > On Fri, Apr 5, 2024 at 7:03 AM Jonathan Cameron > > wrote: > >> > >> On Fri, 5 Apr 2024 00:07:06 + > >> "Ho-Ren (Jack) Chuang" wrote: > >> > >> > The current implementation treats emulated memory

Re: [PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

"Ho-Ren (Jack) Chuang" writes: > On Fri, Apr 5, 2024 at 7:03 AM Jonathan Cameron > wrote: >> >> On Fri, 5 Apr 2024 00:07:06 + >> "Ho-Ren (Jack) Chuang" wrote: >> >> > The current implementation treats emulated memory devices, such as >> > CXL1.1 type3 memory, as normal DRAM when they are

Re: [External] Re: [PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

Hi Jonathan, On Tue, Apr 9, 2024 at 9:12 AM Jonathan Cameron wrote: > > On Fri, 5 Apr 2024 15:43:47 -0700 > "Ho-Ren (Jack) Chuang" wrote: > > > On Fri, Apr 5, 2024 at 7:03 AM Jonathan Cameron > > wrote: > > > > > > On Fri, 5 Apr 2024 00:07:06 + > > > "Ho-Ren (Jack) Chuang" wrote: > > > >

Re: [PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

On Fri, 5 Apr 2024 15:43:47 -0700 "Ho-Ren (Jack) Chuang" wrote: > On Fri, Apr 5, 2024 at 7:03 AM Jonathan Cameron > wrote: > > > > On Fri, 5 Apr 2024 00:07:06 + > > "Ho-Ren (Jack) Chuang" wrote: > > > > > The current implementation treats emulated memory devices, such as > > > CXL1.1

Re: [PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

On Fri, Apr 5, 2024 at 7:03 AM Jonathan Cameron wrote: > > On Fri, 5 Apr 2024 00:07:06 + > "Ho-Ren (Jack) Chuang" wrote: > > > The current implementation treats emulated memory devices, such as > > CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory > >

Re: [PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

On Fri, 5 Apr 2024 00:07:06 + "Ho-Ren (Jack) Chuang" wrote: > The current implementation treats emulated memory devices, such as > CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory > (E820_TYPE_RAM). However, these emulated devices have different > characteristics

[PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

The current implementation treats emulated memory devices, such as CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory (E820_TYPE_RAM). However, these emulated devices have different characteristics than traditional DRAM, making it important to distinguish them. Thus, we