RE: [PATCH v2] ARM: dts: exynos4412-odroidu3: Enable SPI1.

Krzysztof Kozlowski wrote: > > W dniu 13.08.2015 o 18:06, Alexis Ballier pisze: > > SPI1 is available on IO Port #2 (as depicted on their website) in > > PCB Revision 0.5 of Hardkernel Odroid U3 board. > > The shield connects a 256KiB spi-nor flash on that bus. > > > > Signed-off-by: Alexis

Re: [PATCH v2] ARM: dts: exynos4412-odroidu3: Enable SPI1.

W dniu 13.08.2015 o 18:06, Alexis Ballier pisze: > SPI1 is available on IO Port #2 (as depicted on their website) in > PCB Revision 0.5 of Hardkernel Odroid U3 board. > The shield connects a 256KiB spi-nor flash on that bus. > > Signed-off-by: Alexis Ballier > > --- > > Changes in v2: Use

[PATCH v2] ARM: dts: exynos4412-odroidu3: Enable SPI1.

SPI1 is available on IO Port #2 (as depicted on their website) in PCB Revision 0.5 of Hardkernel Odroid U3 board. The shield connects a 256KiB spi-nor flash on that bus. Signed-off-by: Alexis Ballier --- Changes in v2: Use GPIO_ACTIVE_HIGH (Krzysztof Kozlowski)

[PATCH v2] ARM: dts: exynos4412-odroidu3: Enable SPI1.

SPI1 is available on IO Port #2 (as depicted on their website) in PCB Revision 0.5 of Hardkernel Odroid U3 board. The shield connects a 256KiB spi-nor flash on that bus. Signed-off-by: Alexis Ballier aball...@gentoo.org --- Changes in v2: Use GPIO_ACTIVE_HIGH (Krzysztof Kozlowski)

RE: [PATCH v2] ARM: dts: exynos4412-odroidu3: Enable SPI1.

Krzysztof Kozlowski wrote: W dniu 13.08.2015 o 18:06, Alexis Ballier pisze: SPI1 is available on IO Port #2 (as depicted on their website) in PCB Revision 0.5 of Hardkernel Odroid U3 board. The shield connects a 256KiB spi-nor flash on that bus. Signed-off-by: Alexis Ballier

Re: [PATCH v2] ARM: dts: exynos4412-odroidu3: Enable SPI1.

W dniu 13.08.2015 o 18:06, Alexis Ballier pisze: SPI1 is available on IO Port #2 (as depicted on their website) in PCB Revision 0.5 of Hardkernel Odroid U3 board. The shield connects a 256KiB spi-nor flash on that bus. Signed-off-by: Alexis Ballier aball...@gentoo.org --- Changes in