On Thu, Jan 29, 2015 at 04:44:19PM +0100, Matthias Brugger wrote:
> 2015-01-29 15:27 GMT+01:00 Sascha Hauer :
> > On Thu, Jan 29, 2015 at 01:39:42PM +0100, Matthias Brugger wrote:
> >> Hi Sascha,
> >>
> >> 2015-01-26 12:47 GMT+01:00 Sascha Hauer :
> >> > Olof, Arnd,
> >> >
> >> > OK to put the driv
2015-01-29 15:27 GMT+01:00 Sascha Hauer :
> On Thu, Jan 29, 2015 at 01:39:42PM +0100, Matthias Brugger wrote:
>> Hi Sascha,
>>
>> 2015-01-26 12:47 GMT+01:00 Sascha Hauer :
>> > Olof, Arnd,
>> >
>> > OK to put the driver into drivers/soc/mediatek? Can you take these
>> > patches?
>>
>> How does this
On Thu, Jan 29, 2015 at 01:39:42PM +0100, Matthias Brugger wrote:
> Hi Sascha,
>
> 2015-01-26 12:47 GMT+01:00 Sascha Hauer :
> > Olof, Arnd,
> >
> > OK to put the driver into drivers/soc/mediatek? Can you take these
> > patches?
>
> How does this patches fit together with the one James clock fram
2015-01-29 13:39 GMT+01:00 Matthias Brugger :
> Hi Sascha,
>
> 2015-01-26 12:47 GMT+01:00 Sascha Hauer :
>> Olof, Arnd,
>>
>> OK to put the driver into drivers/soc/mediatek? Can you take these
>> patches?
>
> How does this patches fit together with the one James clock framework patches?
I forgot t
Hi Sascha,
2015-01-26 12:47 GMT+01:00 Sascha Hauer :
> Olof, Arnd,
>
> OK to put the driver into drivers/soc/mediatek? Can you take these
> patches?
How does this patches fit together with the one James clock framework patches?
Both use the same compatible "mediatek,mt8135-infracfg" and
"mediatek
Olof, Arnd,
OK to put the driver into drivers/soc/mediatek? Can you take these
patches?
Sascha
On Fri, Jan 23, 2015 at 03:09:55PM +0100, Sascha Hauer wrote:
> This series adds initial support for the MediaTek MT6397 PMIC and the
> necessary infrastructure to attach it on the MT8135 / MT8173 SoCs
This series adds initial support for the MediaTek MT6397 PMIC and the
necessary infrastructure to attach it on the MT8135 / MT8173 SoCs.
The infrastructure includes:
- pericfg / infracfg controller support
The pericfg / infracfg controllers contain miscellaneous registers for
reset controller
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