Hi Stephen,
On Wed, 2017-04-19 at 09:49 -0700, sb...@codeaurora.org wrote:
> On 04/05, Vlad Zakharov wrote:
> >
> > Hi Stephen,
> >
> > On Tue, 2017-04-04 at 18:35 -0700, Stephen Boyd wrote:
> > >
> > > >
> > > > + .pll_table = (struct pll_of_table []){
> > > > + {
> > > > +
Hi Stephen,
On Wed, 2017-04-19 at 09:49 -0700, sb...@codeaurora.org wrote:
> On 04/05, Vlad Zakharov wrote:
> >
> > Hi Stephen,
> >
> > On Tue, 2017-04-04 at 18:35 -0700, Stephen Boyd wrote:
> > >
> > > >
> > > > + .pll_table = (struct pll_of_table []){
> > > > + {
> > > > +
On 04/05, Vlad Zakharov wrote:
> Hi Stephen,
>
> On Tue, 2017-04-04 at 18:35 -0700, Stephen Boyd wrote:
> > > + .pll_table = (struct pll_of_table []){
> > > + {
> > > + .prate = 2700,
> >
> > Can this be another clk in the framework instead of hardcoding
>
On 04/05, Vlad Zakharov wrote:
> Hi Stephen,
>
> On Tue, 2017-04-04 at 18:35 -0700, Stephen Boyd wrote:
> > > + .pll_table = (struct pll_of_table []){
> > > + {
> > > + .prate = 2700,
> >
> > Can this be another clk in the framework instead of hardcoding
>
Hi Stephen,
On Tue, 2017-04-04 at 18:35 -0700, Stephen Boyd wrote:
> > + .pll_table = (struct pll_of_table []){
> > + {
> > + .prate = 2700,
>
> Can this be another clk in the framework instead of hardcoding
> the parent rate?
In fact there is another clk
Hi Stephen,
On Tue, 2017-04-04 at 18:35 -0700, Stephen Boyd wrote:
> > + .pll_table = (struct pll_of_table []){
> > + {
> > + .prate = 2700,
>
> Can this be another clk in the framework instead of hardcoding
> the parent rate?
In fact there is another clk
On 02/21, Vlad Zakharov wrote:
> diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt
> b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt
> new file mode 100644
> index 000..5706246
> --- /dev/null
> +++
On 02/21, Vlad Zakharov wrote:
> diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt
> b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt
> new file mode 100644
> index 000..5706246
> --- /dev/null
> +++
Hi Vlad,
On 21-02-2017 13:11, Vlad Zakharov wrote:
> AXS10X boards manages it's clocks using various PLLs. These PLL has same
> dividers and corresponding control registers mapped to different addresses.
> So we add one common driver for such PLLs.
>
> Each PLL on AXS10X board consist of three
Hi Vlad,
On 21-02-2017 13:11, Vlad Zakharov wrote:
> AXS10X boards manages it's clocks using various PLLs. These PLL has same
> dividers and corresponding control registers mapped to different addresses.
> So we add one common driver for such PLLs.
>
> Each PLL on AXS10X board consist of three
Hi Stephen, Michael,
On Fri, 2017-03-03 at 15:50 -0800, Stephen Boyd wrote:
> On 03/03, Vlad Zakharov wrote:
> >
> > Hi Michael, Stephen,
> >
> > On Tue, 2017-02-21 at 16:11 +0300, Vlad Zakharov wrote:
> > >
> > > AXS10X boards manages it's clocks using various PLLs. These PLL has same
> > >
Hi Stephen, Michael,
On Fri, 2017-03-03 at 15:50 -0800, Stephen Boyd wrote:
> On 03/03, Vlad Zakharov wrote:
> >
> > Hi Michael, Stephen,
> >
> > On Tue, 2017-02-21 at 16:11 +0300, Vlad Zakharov wrote:
> > >
> > > AXS10X boards manages it's clocks using various PLLs. These PLL has same
> > >
On 03/03, Vlad Zakharov wrote:
> Hi Michael, Stephen,
>
> On Tue, 2017-02-21 at 16:11 +0300, Vlad Zakharov wrote:
> > AXS10X boards manages it's clocks using various PLLs. These PLL has same
> > dividers and corresponding control registers mapped to different addresses.
> > So we add one common
On 03/03, Vlad Zakharov wrote:
> Hi Michael, Stephen,
>
> On Tue, 2017-02-21 at 16:11 +0300, Vlad Zakharov wrote:
> > AXS10X boards manages it's clocks using various PLLs. These PLL has same
> > dividers and corresponding control registers mapped to different addresses.
> > So we add one common
Hi Michael, Stephen,
On Tue, 2017-02-21 at 16:11 +0300, Vlad Zakharov wrote:
> AXS10X boards manages it's clocks using various PLLs. These PLL has same
> dividers and corresponding control registers mapped to different addresses.
> So we add one common driver for such PLLs.
>
> Each PLL on
Hi Michael, Stephen,
On Tue, 2017-02-21 at 16:11 +0300, Vlad Zakharov wrote:
> AXS10X boards manages it's clocks using various PLLs. These PLL has same
> dividers and corresponding control registers mapped to different addresses.
> So we add one common driver for such PLLs.
>
> Each PLL on
AXS10X boards manages it's clocks using various PLLs. These PLL has same
dividers and corresponding control registers mapped to different addresses.
So we add one common driver for such PLLs.
Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and
ODIV. Output clock value is managed
AXS10X boards manages it's clocks using various PLLs. These PLL has same
dividers and corresponding control registers mapped to different addresses.
So we add one common driver for such PLLs.
Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and
ODIV. Output clock value is managed
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