Re: [PATCH v2] clk: Add clk_composite_set_rate_and_parent

2016-04-15 Thread Stephen Boyd
On 04/12, Finlye Xiao wrote: > From: Finley Xiao > > When changing the clock-rate, currently a new parent is set first and a > divider adapted thereafter. This may result in the clock-rate overflowing > its target rate for a short time if the new parent has a higher rate than > the old parent. >

[PATCH v2] clk: Add clk_composite_set_rate_and_parent

2016-04-12 Thread Finlye Xiao
From: Finley Xiao When changing the clock-rate, currently a new parent is set first and a divider adapted thereafter. This may result in the clock-rate overflowing its target rate for a short time if the new parent has a higher rate than the old parent. While this often doesn't produce negative