Re: [RESEND PATCH v2] clk: hisilicon: add CRG driver for Hi3798CV200 SoC

2016-10-27 Thread Jiancheng Xue
在 2016/10/28 8:25, Stephen Boyd 写道: > On 10/27, Rob Herring wrote: >> On Fri, Oct 21, 2016 at 09:37:10AM +0800, Jiancheng Xue wrote: >>> Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset >>> Generator) module generates clock and reset signals used >>> by other module blocks on SoC. >>> >>>

Re: [RESEND PATCH v2] clk: hisilicon: add CRG driver for Hi3798CV200 SoC

2016-10-27 Thread Stephen Boyd
On 10/27, Rob Herring wrote: > On Fri, Oct 21, 2016 at 09:37:10AM +0800, Jiancheng Xue wrote: > > Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset > > Generator) module generates clock and reset signals used > > by other module blocks on SoC. > > > > Signed-off-by: Jiancheng Xue > > --- >

Re: [RESEND PATCH v2] clk: hisilicon: add CRG driver for Hi3798CV200 SoC

2016-10-27 Thread Rob Herring
On Fri, Oct 21, 2016 at 09:37:10AM +0800, Jiancheng Xue wrote: > Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset > Generator) module generates clock and reset signals used > by other module blocks on SoC. > > Signed-off-by: Jiancheng Xue > --- > change log > v2: > - Fixed compiling error

[RESEND PATCH v2] clk: hisilicon: add CRG driver for Hi3798CV200 SoC

2016-10-20 Thread Jiancheng Xue
Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: Jiancheng Xue --- change log v2: - Fixed compiling error when compiled as a module. - Fixed issues pointed by Stephen Boyd. - Added prefix

Re: [PATCH v2] clk: hisilicon: add CRG driver for Hi3798CV200 SoC

2016-10-10 Thread Jiancheng Xue
在 2016/9/24 9:45, Jiancheng Xue 写道: > 在 2016/9/24 1:47, Rob Herring 写道: >> On Sun, Sep 18, 2016 at 03:30:21PM +0800, Jiancheng Xue wrote: >>> Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset >>> Generator) module generates clock and reset signals used >>> by other module blocks on SoC. >>>

Re: [PATCH v2] clk: hisilicon: add CRG driver for Hi3798CV200 SoC

2016-09-23 Thread Jiancheng Xue
在 2016/9/24 1:47, Rob Herring 写道: > On Sun, Sep 18, 2016 at 03:30:21PM +0800, Jiancheng Xue wrote: >> Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset >> Generator) module generates clock and reset signals used >> by other module blocks on SoC. >> >> Signed-off-by: Jiancheng Xue >> --- >> c

Re: [PATCH v2] clk: hisilicon: add CRG driver for Hi3798CV200 SoC

2016-09-23 Thread Rob Herring
On Sun, Sep 18, 2016 at 03:30:21PM +0800, Jiancheng Xue wrote: > Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset > Generator) module generates clock and reset signals used > by other module blocks on SoC. > > Signed-off-by: Jiancheng Xue > --- > change log > v2: > - Fixed compiling error

[PATCH v2] clk: hisilicon: add CRG driver for Hi3798CV200 SoC

2016-09-18 Thread Jiancheng Xue
Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: Jiancheng Xue --- change log v2: - Fixed compiling error when compiled as a module. - Fixed issues pointed by Stephen Boyd. - Added prefix