08.07.2020 10:46, Dmitry Osipenko пишет:
> - return val & PLL_BASE_ENABLE ? 1 : 0;
> + return val & PLL_BASE_ENABLE;
This was unintended change that caught my eve only after sending out the
email, woops :) Please let me make a v3 shortly.
Power Management Controller (PMC) can override the PLLM clock settings,
including the enable-state. Although PMC could only act as a second level
gate, meaning that PLLM needs to be enabled by the Clock and Reset
Controller (CaR) anyways if we want it to be enabled. Hence, when PLLM is
overridden b
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