Re: [PATCH v2] driver: aspeed: g6: Fix PWMG0 pinctrl setting

Hi Andrew, Best Regards, Billy Tsai On 2020/12/17, 8:38 AM, Andrew Jeffery wrote: > The SCU offset for signal PWM8 in group PWM8G0 is wrong, fix it from > SCU414 to SCU4B4. > Besides that, When PWM8~15 of PWMG0 set it needs to clear SCU414 bits > at the same time. FYI,

Re: [PATCH v2] driver: aspeed: g6: Fix PWMG0 pinctrl setting

> The SCU offset for signal PWM8 in group PWM8G0 is wrong, fix it from > SCU414 to SCU4B4. > Besides that, When PWM8~15 of PWMG0 set it needs to clear SCU414 bits > at the same time. FYI, we don't need to explicitly clear SCU414[...] as part of the PWM mux configuration as the these bits are

[PATCH v2] driver: aspeed: g6: Fix PWMG0 pinctrl setting

The SCU offset for signal PWM8 in group PWM8G0 is wrong, fix it from SCU414 to SCU4B4. Besides that, When PWM8~15 of PWMG0 set it needs to clear SCU414 bits at the same time. Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Billy Tsai ---