Re: [PATCH v2] drm/vc4: Fix sleeps during the IRQ handler for DSI transactions.

2017-10-14 Thread Paul Menzel
Dear Eric, Some nit picks where stuff contradicts the coding style. Am Freitag, den 13.10.2017, 17:12 -0700 schrieb Eric Anholt: > VC4's DSI1 has a bug where the AXI connection is broken for 32-bit > writes from the CPU, so we use the DMA engine to DMA 32-bit values > into registers instead.

Re: [PATCH v2] drm/vc4: Fix sleeps during the IRQ handler for DSI transactions.

2017-10-14 Thread Paul Menzel
Dear Eric, Some nit picks where stuff contradicts the coding style. Am Freitag, den 13.10.2017, 17:12 -0700 schrieb Eric Anholt: > VC4's DSI1 has a bug where the AXI connection is broken for 32-bit > writes from the CPU, so we use the DMA engine to DMA 32-bit values > into registers instead.

Re: [PATCH v2] drm/vc4: Fix sleeps during the IRQ handler for DSI transactions.

2017-10-14 Thread Boris Brezillon
On Fri, 13 Oct 2017 17:12:55 -0700 Eric Anholt wrote: > VC4's DSI1 has a bug where the AXI connection is broken for 32-bit > writes from the CPU, so we use the DMA engine to DMA 32-bit values > into registers instead. That sleeps, so we can't do it from the top > half. > > As

Re: [PATCH v2] drm/vc4: Fix sleeps during the IRQ handler for DSI transactions.

2017-10-14 Thread Boris Brezillon
On Fri, 13 Oct 2017 17:12:55 -0700 Eric Anholt wrote: > VC4's DSI1 has a bug where the AXI connection is broken for 32-bit > writes from the CPU, so we use the DMA engine to DMA 32-bit values > into registers instead. That sleeps, so we can't do it from the top > half. > > As a solution, use

[PATCH v2] drm/vc4: Fix sleeps during the IRQ handler for DSI transactions.

2017-10-13 Thread Eric Anholt
VC4's DSI1 has a bug where the AXI connection is broken for 32-bit writes from the CPU, so we use the DMA engine to DMA 32-bit values into registers instead. That sleeps, so we can't do it from the top half. As a solution, use an interrupt thread so that all our writes happen when sleeping is is

[PATCH v2] drm/vc4: Fix sleeps during the IRQ handler for DSI transactions.

2017-10-13 Thread Eric Anholt
VC4's DSI1 has a bug where the AXI connection is broken for 32-bit writes from the CPU, so we use the DMA engine to DMA 32-bit values into registers instead. That sleeps, so we can't do it from the top half. As a solution, use an interrupt thread so that all our writes happen when sleeping is is