Marc,
On Thu, 18 Feb 2016 16:41:23 +, Marc Zyngier wrote:
> It looks really nice, except for a couple of points, see below.
Thanks again for the review.
> > +/*
> > + * We don't support the group events, so we simply have 8 interrupts
> > + * per frame.
> > + */
> > +#define NODMIS_PER_FRAM
Hey Thomas,
It looks really nice, except for a couple of points, see below.
On 18/02/16 15:58, Thomas Petazzoni wrote:
> This commits adds a new irqchip driver that handles the ODMI
> controller found on Marvell 7K/8K processors. The ODMI controller
> provide MSI interrupt functionality to on-boa
On Thursday 18 February 2016 17:16:23 Thomas Petazzoni wrote:
>
> On Thu, 18 Feb 2016 17:08:05 +0100, Arnd Bergmann wrote:
> > On Thursday 18 February 2016 16:58:54 Thomas Petazzoni wrote:
> > > +- marvell,spi-base : List of GIC base SPI interrupts, one for each
> > > +
Arnd,
On Thu, 18 Feb 2016 17:08:05 +0100, Arnd Bergmann wrote:
> On Thursday 18 February 2016 16:58:54 Thomas Petazzoni wrote:
> > +- marvell,spi-base : List of GIC base SPI interrupts, one for each
> > + ODMI frame. Those SPI interrupts are 0-based,
> > +
On Thursday 18 February 2016 16:58:54 Thomas Petazzoni wrote:
> +- marvell,spi-base : List of GIC base SPI interrupts, one for each
> + ODMI frame. Those SPI interrupts are 0-based,
> + i.e marvell,spi-base = <128> will use SPI #96.
> +
This commits adds a new irqchip driver that handles the ODMI
controller found on Marvell 7K/8K processors. The ODMI controller
provide MSI interrupt functionality to on-board peripherals, much like
the GIC-v2m.
Signed-off-by: Thomas Petazzoni
---
Changes v1 -> v2:
- Better commit title, as sugge
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