Re: [PATCH v2] mmc: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

On 4 November 2014 08:32, Vincent Wan wrote: > SDHC controller in AMD chipsets require SDHC transfer mode > register to be cleared for commands without data. The issue was > uncovered during testing eMMC cards on KB/ML based platforms. > > Signed-off-by: Vincent Wan > Signed-off-by: Arindam Nath

[PATCH v2] mmc: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

SDHC controller in AMD chipsets require SDHC transfer mode register to be cleared for commands without data. The issue was uncovered during testing eMMC cards on KB/ML based platforms. Signed-off-by: Vincent Wan Signed-off-by: Arindam Nath Cc: Huang Rui Tested-by: Vikram B Tested-by:

[PATCH v2] mmc: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

SDHC controller in AMD chipsets require SDHC transfer mode register to be cleared for commands without data. The issue was uncovered during testing eMMC cards on KB/ML based platforms. Signed-off-by: Vincent Wan vincent@amd.com Signed-off-by: Arindam Nath arindam.n...@amd.com Cc: Huang Rui

Re: [PATCH v2] mmc: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

On 4 November 2014 08:32, Vincent Wan vincent@amd.com wrote: SDHC controller in AMD chipsets require SDHC transfer mode register to be cleared for commands without data. The issue was uncovered during testing eMMC cards on KB/ML based platforms. Signed-off-by: Vincent Wan