On Thu, 8 Aug 2019, Bjorn Helgaas wrote:
> Indeed, sorry I missed it. I generally work based on -rc1, and it
> looks like 251a44888183 was merged after -rc1.
>
> Since we're after the merge window, the default target would be v5.4,
> but I see some post-rc1 pull requests from you, so if you need
On Thu, Aug 08, 2019 at 01:51:50PM -0700, Paul Walmsley wrote:
> On Thu, 8 Aug 2019, Bjorn Helgaas wrote:
> > On Thu, Jul 25, 2019 at 02:28:07PM -0700, Paul Walmsley wrote:
> > > From: Wesley Terpstra
> > >
> > > This is part of adding support for RISC-V systems with PCIe host
> > > controllers
Hi Bjorn,
On Thu, 8 Aug 2019, Bjorn Helgaas wrote:
> On Thu, Jul 25, 2019 at 02:28:07PM -0700, Paul Walmsley wrote:
> > From: Wesley Terpstra
> >
> > This is part of adding support for RISC-V systems with PCIe host
> > controllers that support message-signaled interrupts.
> >
> > Signed-off-b
Hi Paul, Wesley,
On Thu, Jul 25, 2019 at 02:28:07PM -0700, Paul Walmsley wrote:
> From: Wesley Terpstra
>
> This is part of adding support for RISC-V systems with PCIe host
> controllers that support message-signaled interrupts.
>
> Signed-off-by: Wesley Terpstra
> [paul.walms...@sifive.com:
On Fri, Jul 26, 2019 at 5:28 AM Paul Walmsley wrote:
>
> From: Wesley Terpstra
>
> This is part of adding support for RISC-V systems with PCIe host
> controllers that support message-signaled interrupts.
>
> Signed-off-by: Wesley Terpstra
> [paul.walms...@sifive.com: wrote patch description; spl
From: Wesley Terpstra
This is part of adding support for RISC-V systems with PCIe host
controllers that support message-signaled interrupts.
Signed-off-by: Wesley Terpstra
[paul.walms...@sifive.com: wrote patch description; split this
patch from the arch/riscv patch]
Signed-off-by: Paul Walms
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