Re: [PATCH v2] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2

On Thu, 25 Aug, at 05:35:14AM, Borislav Petkov wrote: > (dropping stable@ from CC) > > On Wed, Aug 24, 2016 at 08:27:06PM +0200, Peter Zijlstra wrote: > > They're not meant to be comparable between machines. I wouldn't even > > compare the LLC numbers between two different Intel parts. > > > > Th

Re: [PATCH v2] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2

(dropping stable@ from CC) On Wed, Aug 24, 2016 at 08:27:06PM +0200, Peter Zijlstra wrote: > They're not meant to be comparable between machines. I wouldn't even > compare the LLC numbers between two different Intel parts. > > These events are meant to profile a workload on the machine you run th

Re: [PATCH v2] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2

On Wed, Aug 24, 2016 at 04:55:14PM +0200, Borislav Petkov wrote: > On Wed, Aug 24, 2016 at 02:12:08PM +0100, Matt Fleming wrote: > > While the Intel PMU monitors the LLC when perf enables the > > HW_CACHE_REFERENCES and HW_CACHE_MISSES events, these events monitor > > L1 instruction cache fetches (

Re: [PATCH v2] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2

On Wed, Aug 24, 2016 at 02:12:08PM +0100, Matt Fleming wrote: > While the Intel PMU monitors the LLC when perf enables the > HW_CACHE_REFERENCES and HW_CACHE_MISSES events, these events monitor > L1 instruction cache fetches (0x0080) and instruction cache misses > (0x0081) on the AMD PMU. > > This

[PATCH v2] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2

While the Intel PMU monitors the LLC when perf enables the HW_CACHE_REFERENCES and HW_CACHE_MISSES events, these events monitor L1 instruction cache fetches (0x0080) and instruction cache misses (0x0081) on the AMD PMU. This is extremely confusing when monitoring the same workload across Intel and