* Mika Westerberg wrote:
> On Wed, Jan 29, 2014 at 01:47:54PM -0800, Bin Gao wrote:
> > On Tue, Jan 28, 2014 at 02:04:07PM +0200, Mika Westerberg wrote:
> > > Actually it does not work. I had the fallback path still in the patch when
> > > I tried.
> >
> > Let's merge the ptach v2
* Mika Westerberg mika.westerb...@linux.intel.com wrote:
On Wed, Jan 29, 2014 at 01:47:54PM -0800, Bin Gao wrote:
On Tue, Jan 28, 2014 at 02:04:07PM +0200, Mika Westerberg wrote:
Actually it does not work. I had the fallback path still in the patch when
I tried.
Let's merge the
On Wed, Jan 29, 2014 at 01:47:54PM -0800, Bin Gao wrote:
> On Tue, Jan 28, 2014 at 02:04:07PM +0200, Mika Westerberg wrote:
> > Actually it does not work. I had the fallback path still in the patch when
> > I tried.
>
> Let's merge the ptach v2 then(continue on msr calibration retuning 0).
> All
On Wed, Jan 29, 2014 at 01:47:54PM -0800, Bin Gao wrote:
On Tue, Jan 28, 2014 at 02:04:07PM +0200, Mika Westerberg wrote:
Actually it does not work. I had the fallback path still in the patch when
I tried.
Let's merge the ptach v2 then(continue on msr calibration retuning 0).
All
On Tue, Jan 28, 2014 at 02:04:07PM +0200, Mika Westerberg wrote:
> Actually it does not work. I had the fallback path still in the patch when
> I tried.
Let's merge the ptach v2 then(continue on msr calibration retuning 0).
All supported SoCs now have the correct frequency ID coding
so continuing
On Tue, Jan 28, 2014 at 02:04:07PM +0200, Mika Westerberg wrote:
Actually it does not work. I had the fallback path still in the patch when
I tried.
Let's merge the ptach v2 then(continue on msr calibration retuning 0).
All supported SoCs now have the correct frequency ID coding
so continuing
On Mon, Jan 27, 2014 at 12:20:02PM +0200, Mika Westerberg wrote:
> On Sat, Jan 25, 2014 at 01:09:23AM -0800, Bin Gao wrote:
> > > diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index
> > > a3acbac2ee72$
> > > --- a/arch/x86/kernel/tsc.c
> > > +++ b/arch/x86/kernel/tsc.c
> > > @@
On Mon, Jan 27, 2014 at 12:20:02PM +0200, Mika Westerberg wrote:
On Sat, Jan 25, 2014 at 01:09:23AM -0800, Bin Gao wrote:
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index
a3acbac2ee72$
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -655,10 +655,11 @@
On Sat, Jan 25, 2014 at 01:09:23AM -0800, Bin Gao wrote:
> > diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index
> > a3acbac2ee72$
> > --- a/arch/x86/kernel/tsc.c
> > +++ b/arch/x86/kernel/tsc.c
> > @@ -655,10 +655,11 @@ unsigned long native_calibrate_tsc(void)
> >
On Sat, Jan 25, 2014 at 01:09:23AM -0800, Bin Gao wrote:
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index
a3acbac2ee72$
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -655,10 +655,11 @@ unsigned long native_calibrate_tsc(void)
local_irq_save(flags);
> diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index a3acbac2ee72$
> --- a/arch/x86/kernel/tsc.c
> +++ b/arch/x86/kernel/tsc.c
> @@ -655,10 +655,11 @@ unsigned long native_calibrate_tsc(void)
> local_irq_save(flags);
> i = try_msr_calibrate_tsc(_calibrate);
>
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index a3acbac2ee72$
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -655,10 +655,11 @@ unsigned long native_calibrate_tsc(void)
local_irq_save(flags);
i = try_msr_calibrate_tsc(fast_calibrate);
Baytrail is based on Silvermont core so MSR_FSB_FREQ[2:0] == 0 means that
the CPU reference clock runs at 83.3MHz. Without this we crash a bit later
with backtrace looking like:
divide error: [#1] PREEMPT SMP
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Tainted: GW3.13.0+
Baytrail is based on Silvermont core so MSR_FSB_FREQ[2:0] == 0 means that
the CPU reference clock runs at 83.3MHz. Without this we crash a bit later
with backtrace looking like:
divide error: [#1] PREEMPT SMP
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Tainted: GW3.13.0+
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