On Sat, Oct 20, 2018 at 07:41:36PM +0200, Borislav Petkov wrote:
> Dropping stable.
>
> On Sat, Oct 20, 2018 at 07:41:58AM -0700, Andi Kleen wrote:
> > From: Andi Kleen
> >
> > The Intel microcode revision space is unsigned. Inside Intel there are
> > special
> > microcodes that have the
On Sat, Oct 20, 2018 at 07:41:36PM +0200, Borislav Petkov wrote:
> Dropping stable.
>
> On Sat, Oct 20, 2018 at 07:41:58AM -0700, Andi Kleen wrote:
> > From: Andi Kleen
> >
> > The Intel microcode revision space is unsigned. Inside Intel there are
> > special
> > microcodes that have the
Dropping stable.
On Sat, Oct 20, 2018 at 07:41:58AM -0700, Andi Kleen wrote:
> From: Andi Kleen
>
> The Intel microcode revision space is unsigned. Inside Intel there are special
> microcodes that have the highest bit set, and they are considered to have
> a higher revision than any microcodes
Dropping stable.
On Sat, Oct 20, 2018 at 07:41:58AM -0700, Andi Kleen wrote:
> From: Andi Kleen
>
> The Intel microcode revision space is unsigned. Inside Intel there are special
> microcodes that have the highest bit set, and they are considered to have
> a higher revision than any microcodes
From: Andi Kleen
The Intel microcode revision space is unsigned. Inside Intel there are special
microcodes that have the highest bit set, and they are considered to have
a higher revision than any microcodes that don't have this bit set.
The function comparing the microcode revision in the
From: Andi Kleen
The Intel microcode revision space is unsigned. Inside Intel there are special
microcodes that have the highest bit set, and they are considered to have
a higher revision than any microcodes that don't have this bit set.
The function comparing the microcode revision in the
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