Re: [PATCH v2 0/2] tpm: add driver for cr50 on SPI

Hi Peter, > > This patchset adds support for H1 Secure Microcontroller running > > Cr50 firmware. It implements several functions, including TPM-like > > functionality, and communicates over SPI using the FIFO protocol > > described in the PTP Spec, section 6. > > H1 is a proprietary chip that

Re: [PATCH v2 0/2] tpm: add driver for cr50 on SPI

Hi Peter, > > This patchset adds support for H1 Secure Microcontroller running > > Cr50 firmware. It implements several functions, including TPM-like > > functionality, and communicates over SPI using the FIFO protocol > > described in the PTP Spec, section 6. > > H1 is a proprietary chip that

Aw: [PATCH v2 0/2] tpm: add driver for cr50 on SPI

Hi Andrey, thanks for the update. > This patchset adds support for H1 Secure Microcontroller running > Cr50 firmware. It implements several functions, including TPM-like > functionality, and communicates over SPI using the FIFO protocol > described in the PTP Spec, section 6. > H1 is a

Aw: [PATCH v2 0/2] tpm: add driver for cr50 on SPI

Hi Andrey, thanks for the update. > This patchset adds support for H1 Secure Microcontroller running > Cr50 firmware. It implements several functions, including TPM-like > functionality, and communicates over SPI using the FIFO protocol > described in the PTP Spec, section 6. > H1 is a

[PATCH v2 0/2] tpm: add driver for cr50 on SPI

This patchset adds support for H1 Secure Microcontroller running Cr50 firmware. It implements several functions, including TPM-like functionality, and communicates over SPI using the FIFO protocol described in the PTP Spec, section 6. H1 is a proprietary chip that the Chrome OS team is

[PATCH v2 0/2] tpm: add driver for cr50 on SPI

This patchset adds support for H1 Secure Microcontroller running Cr50 firmware. It implements several functions, including TPM-like functionality, and communicates over SPI using the FIFO protocol described in the PTP Spec, section 6. H1 is a proprietary chip that the Chrome OS team is