On Friday 16 November 2012 05:07:53 Thierry Reding wrote:
> This second version of this patch series splits the patches up into more
> logical chunks as requested by Stephen. Instead of renaming the matching
> parameters in the clock driver, this version renames the AUXDATA entries
> to match what
Hi Thierry,
Thank you for your hard work.
The series,
Acked-by: Mark Zhang
Reviewed-by: Mark Zhang
Tested-by: Mark Zhang
On Ventana, LVDS and HDMI worked.
PS: Alex's power sequence patch is needed to enable panel and backlight.
Also we need to define dc and hdmi nodes in tegra20-ventana.
On 11/15/2012 02:07 PM, Thierry Reding wrote:
> This second version of this patch series splits the patches up into more
> logical chunks as requested by Stephen. Instead of renaming the matching
> parameters in the clock driver, this version renames the AUXDATA entries
> to match what the clock dr
This second version of this patch series splits the patches up into more
logical chunks as requested by Stephen. Instead of renaming the matching
parameters in the clock driver, this version renames the AUXDATA entries
to match what the clock driver expects. Furthermore the host1x clock is
initiali
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