Quoting Weiyi Lu (2020-11-08 18:13:15)
> This series is based on v5.10-rc1 and
> [v5,07/24] clk: mediatek: Fix asymmetrical PLL enable and disable control[1]
> in Mediatek MT8192 clock support series
>
> [1]
>
This series is based on v5.10-rc1 and
[v5,07/24] clk: mediatek: Fix asymmetrical PLL enable and disable control[1] in
Mediatek MT8192 clock support series
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/1604887429-29445-8-git-send-email-weiyi...@mediatek.com/
change since v1:
-
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