Hi Sumit,
On 2020-08-11 14:15, Sumit Garg wrote:
Hi Marc,
On Thu, 25 Jun 2020 at 01:28, Marc Zyngier wrote:
For as long as SMP ARM has existed, IPIs have been handled as
something special. The arch code and the interrupt controller exchange
a couple of hooks (one to generate an IPI, another
Hi Marc,
On Thu, 25 Jun 2020 at 01:28, Marc Zyngier wrote:
>
> For as long as SMP ARM has existed, IPIs have been handled as
> something special. The arch code and the interrupt controller exchange
> a couple of hooks (one to generate an IPI, another to handle it).
>
> Although this is perfectly
On 25/06/20 19:24, Valentin Schneider wrote:
> I have a few extra nits/comments in some patches, but it's all fairly minor
> so FWIW you can also add, for patches [01-10, 14-15]:
>
> Reviewed-by: Valentin Schneider
>
> I haven't really looked at those other irqchips, but I can give it a shot
> i
Hi Marc,
On 24/06/20 20:57, Marc Zyngier wrote:
> For as long as SMP ARM has existed, IPIs have been handled as
> something special. The arch code and the interrupt controller exchange
> a couple of hooks (one to generate an IPI, another to handle it).
>
> Although this is perfectly manageable, it
For as long as SMP ARM has existed, IPIs have been handled as
something special. The arch code and the interrupt controller exchange
a couple of hooks (one to generate an IPI, another to handle it).
Although this is perfectly manageable, it prevents the use of features
that we could use if IPIs we
5 matches
Mail list logo
