On Mon, May 18, 2020 at 02:04:53PM +0300, Serge Semin wrote:
> On Mon, May 18, 2020 at 11:51:30AM +0100, Mark Brown wrote:
> > > - semantically the xfer argument isn't optional and we can't fetch it
> > > that easy
> > > in the dmaengine completion callbacks.
> > Not sure I follow this.
> I m
On Fri, May 15, 2020 at 10:40:58PM +0300, Serge Semin wrote:
> On Fri, May 15, 2020 at 03:01:11PM +0300, Andy Shevchenko wrote:
> > On Fri, May 15, 2020 at 01:47:41PM +0300, Serge Semin wrote:
> > > Since DMA transfers are performed asynchronously with actual SPI
> > > transaction, then even if DMA
On Fri, May 15, 2020 at 11:02:50PM +0300, Serge Semin wrote:
> On Fri, May 15, 2020 at 01:41:31PM +0100, Mark Brown wrote:
> > I guess we could, though it's really there because for historical
> > reasons we've got a bunch of different ways of specifying delays from
> > client drivers rather than
On Fri, May 15, 2020 at 03:37:02PM +0300, Andy Shevchenko wrote:
> On Fri, May 15, 2020 at 01:18:15PM +0100, Mark Brown wrote:
> > Well, nobody wrote one.
> spi_delay_exec() seems quite good to be used here.
> Can we use it for delays?
I guess we could, though it's really there because for histo
On Fri, May 15, 2020 at 01:18:15PM +0100, Mark Brown wrote:
> On Fri, May 15, 2020 at 03:01:11PM +0300, Andy Shevchenko wrote:
>
> > General question, doesn't spi core provides us some helpers like
> > spi_delay_exec()?
>
> Well, nobody wrote one.
spi_delay_exec() seems quite good to be used her
On Fri, May 15, 2020 at 03:01:11PM +0300, Andy Shevchenko wrote:
> General question, doesn't spi core provides us some helpers like
> spi_delay_exec()?
Well, nobody wrote one. It's also a bit tricky to handle given that
often you're checking some controller specific things while a FIFO in
the IP
On Fri, May 15, 2020 at 01:47:41PM +0300, Serge Semin wrote:
> Since DMA transfers are performed asynchronously with actual SPI
> transaction, then even if DMA transfers are finished it doesn't mean
> all data is actually pushed to the SPI bus. Some data might still be
> in the controller FIFO. Thi
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