remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask that only used for pll dividers.
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com> --- drivers/clk/mediatek/clk-mt8167.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-mt8167.c index e5ea10e..180e24a 100644 --- a/drivers/clk/mediatek/clk-mt8167.c +++ b/drivers/clk/mediatek/clk-mt8167.c @@ -1016,21 +1016,21 @@ static void __init mtk_infracfg_init(struct device_node *node) }; static const struct mtk_pll_data plls[] = { - PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0x00000001, 0, + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0, 21, 0x0104, 24, 0, 0x0104, 0), - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0x00000001, + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0, HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0), - PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000001, + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000, HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0), - PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0x00000001, 0, + PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0, 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table), - PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0x00000001, 0, + PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0, 31, 0x0180, 1, 0x0194, 0x0184, 0), - PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0x00000001, 0, + PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0, 31, 0x01A0, 1, 0x01B4, 0x01A4, 0), - PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0x00000001, 0, + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0, 0, 21, 0x01C4, 24, 0, 0x01C4, 0), - PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x01E0, 0x01F0, 0x00000001, 0, + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x01E0, 0x01F0, 0, 0, 21, 0x01E4, 24, 0, 0x01E4, 0), }; -- 1.8.1.1.dirty