RE: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic

2021-02-03 Thread Wu, Hao
> On Wed, 3 Feb 2021, Russ Weight wrote: > > > > > > > On 2/3/21 1:28 AM, Wu, Hao wrote: > >>> Subject: Re: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic > >>> > >>> Sorry for the delay on this patch. It seemed like a lower pr

Re: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic

2021-02-03 Thread matthew . gerlach
On Wed, 3 Feb 2021, Russ Weight wrote: On 2/3/21 1:28 AM, Wu, Hao wrote: Subject: Re: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic Sorry for the delay on this patch. It seemed like a lower priority patch than others, since we haven't seen any issues with current pro

Re: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic

2021-02-03 Thread Russ Weight
On 2/3/21 1:28 AM, Wu, Hao wrote: >> Subject: Re: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic >> >> Sorry for the delay on this patch. It seemed like a lower priority patch than >> others, since we haven't seen any issues with current products.

RE: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic

2021-02-03 Thread Wu, Hao
> Subject: Re: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic > > Sorry for the delay on this patch. It seemed like a lower priority patch than > others, since we haven't seen any issues with current products. Please my > responses inline. > > On 9/17

Re: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic

2021-02-02 Thread Russ Weight
On 9/17/20 2:38 PM, Moritz Fischer wrote: > On Thu, Sep 17, 2020 at 01:28:22PM -0700, Tom Rix wrote: >> On 9/17/20 11:32 AM, Russ Weight wrote: >>> Port enable is not complete until ACK = 0. Change >>> __afu_port_enable() to guarantee that the enable process >>> is complete by polling for ACK ==

Re: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic

2021-02-02 Thread Russ Weight
On 2/2/21 12:32 PM, Russ Weight wrote: > > On 9/17/20 1:28 PM, Tom Rix wrote: >> On 9/17/20 11:32 AM, Russ Weight wrote: >>> Port enable is not complete until ACK = 0. Change >>> __afu_port_enable() to guarantee that the enable process >>> is complete by polling for ACK == 0. >>> >>> Signed-off-

Re: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic

2021-02-02 Thread Russ Weight
On 9/17/20 1:28 PM, Tom Rix wrote: > On 9/17/20 11:32 AM, Russ Weight wrote: >> Port enable is not complete until ACK = 0. Change >> __afu_port_enable() to guarantee that the enable process >> is complete by polling for ACK == 0. >> >> Signed-off-by: Russ Weight >> --- >> drivers/fpga/dfl-afu-

Re: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic

2021-02-02 Thread Russ Weight
September 18, 2020 2:32 AM >> To: m...@kernel.org; linux-f...@vger.kernel.org; linux- >> ker...@vger.kernel.org >> Cc: t...@redhat.com; lgonc...@redhat.com; Xu, Yilun ; >> Wu, Hao ; Gerlach, Matthew >> ; Weight, Russell H >> >> Subject: [PATCH v2 1/1]

RE: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic

2020-09-17 Thread Wu, Hao
> Subject: Re: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic > > On Thu, Sep 17, 2020 at 01:28:22PM -0700, Tom Rix wrote: > > > > On 9/17/20 11:32 AM, Russ Weight wrote: > > > Port enable is not complete until ACK = 0. Change > > > __afu_por

RE: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic

2020-09-17 Thread Wu, Hao
, Russell H > > Subject: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic > > Port enable is not complete until ACK = 0. Change > __afu_port_enable() to guarantee that the enable process > is complete by polling for ACK == 0. The description of this port reset ack bit is

Re: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic

2020-09-17 Thread Xu Yilun
> > > /** > > > * __afu_port_enable - enable a port by clear reset > > > * @pdev: port platform device. > > > @@ -32,7 +35,7 @@ > > > * > > > * The caller needs to hold lock for protection. > > > */ > > > -void __afu_port_enable(struct platform_device *pdev) > > > +int __afu_port_enable(

Re: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic

2020-09-17 Thread Moritz Fischer
On Thu, Sep 17, 2020 at 01:28:22PM -0700, Tom Rix wrote: > > On 9/17/20 11:32 AM, Russ Weight wrote: > > Port enable is not complete until ACK = 0. Change > > __afu_port_enable() to guarantee that the enable process > > is complete by polling for ACK == 0. > > > > Signed-off-by: Russ Weight Gener

Re: [PATCH v2 1/1] fpga: dfl: afu: harden port enable logic

2020-09-17 Thread Tom Rix
On 9/17/20 11:32 AM, Russ Weight wrote: > Port enable is not complete until ACK = 0. Change > __afu_port_enable() to guarantee that the enable process > is complete by polling for ACK == 0. > > Signed-off-by: Russ Weight > --- > drivers/fpga/dfl-afu-error.c | 2 +- > drivers/fpga/dfl-afu-main.

[PATCH v2 1/1] fpga: dfl: afu: harden port enable logic

2020-09-17 Thread Russ Weight
Port enable is not complete until ACK = 0. Change __afu_port_enable() to guarantee that the enable process is complete by polling for ACK == 0. Signed-off-by: Russ Weight --- drivers/fpga/dfl-afu-error.c | 2 +- drivers/fpga/dfl-afu-main.c | 29 + drivers/fpga/dfl-a