[PATCH v2 1/2] arm64: dts: ti: k3-j7200-som-p0: main_i2c0 have an ioexpander on the SOM

[Peter Ujfalusi]

The J7200 SOM have additional io expander which is used to control several
SOM level muxes to make sure that the correct signals are routed to the
correct pin on the SOM <-> CPB connectors.

Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
Reviewed-by: Vignesh Raghavendra <vigne...@ti.com>
---
 .../dts/ti/k3-j7200-common-proc-board.dts     | 11 --------
 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi   | 26 +++++++++++++++++++
 2 files changed, 26 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts 
b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 6b3863108571..2721137d8943 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -43,13 +43,6 @@ J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) 
MCU_MDIO0_MDIO */
 };
 
 &main_pmx0 {
-       main_i2c0_pins_default: main-i2c0-pins-default {
-               pinctrl-single,pins = <
-                       J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL 
*/
-                       J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA 
*/
-               >;
-       };
-
        main_i2c1_pins_default: main-i2c1-pins-default {
                pinctrl-single,pins = <
                        J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) 
ECAP0_IN_APWM_OUT.I2C1_SCL */
@@ -146,10 +139,6 @@ &cpsw_port1 {
 };
 
 &main_i2c0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&main_i2c0_pins_default>;
-       clock-frequency = <400000>;
-
        exp1: gpio@20 {
                compatible = "ti,tca6416";
                reg = <0x20>;
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi 
b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
index fbd17d38f6b6..7b5e9aa0324e 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
@@ -48,6 +48,15 @@ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) 
MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
        };
 };
 
+&main_pmx0 {
+       main_i2c0_pins_default: main-i2c0-pins-default {
+               pinctrl-single,pins = <
+                       J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL 
*/
+                       J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA 
*/
+               >;
+       };
+};
+
 &hbmc {
        /* OSPI and HBMC are muxed inside FSS, Bootloader will enable
         * appropriate node based on board detection
@@ -131,3 +140,20 @@ &mailbox0_cluster10 {
 &mailbox0_cluster11 {
        status = "disabled";
 };
+
+&main_i2c0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_i2c0_pins_default>;
+       clock-frequency = <400000>;
+
+       exp_som: gpio@21 {
+               compatible = "ti,tca6408";
+               reg = <0x21>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
+                                 "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
+                                 "UART/LIN_MUX_SEL", 
"TRC_D17/AUDIO_REFCLK_SEL",
+                                 "GPIO_LIN_EN", "CAN_STB";
+       };
+};
-- 
Peter

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